Fiber-optic communication faces challenges to address impairment such as chromatic dispersion, which distorts signals, necessitating efficient chromatic dispersion compensation (CDC) solutions. In this work, architectural trade-offs when implementing finite-length impulse response (FIR) filters in the frequency-domain for high-speed CDC is presented. Most earlier works have considered a fully parallel FFT. However, as shown in this work, it is possible to reduce the power consumption by increasing the FFTs size, leading to time-multiplexed streaming FFT architectures. The results, implemented for a tentative 400G 16-QAM system, illustrates that traditionally used complexity measures, such as number of multiplications per sample, are not suitable when determining the best FFT size. It is also shown that this size is not necessarily a power of two. Instead, a ratio between the block length and the filter length of between one and two provides the best results in this case, lower than the commonly used multiplications per sample estimate. The results highlights the impact of the data shuffling, required for time-multiplexed FFTs, on the power consumption, but also the possibilities to lower the power consumption by not restricting to power-of-two FFTs.

A new Python library, APyTypes, suitable for simulating and exploring finite word-length effects is presented. The library supports configurable bit-accurate fixed- and floating-point types of both scalars and multidimensional arrays and uses a C++ backend to accelerate runtime performance. The underlying design principles of the library are introduced and examples show how it can be used. We argue that APyTypes have significant advantages over existing arithmetic libraries, especially from a hardware design perspective. Finally, some directions for further work are outlined.

A modern communication testbed based on distributed multiple-input multiple-output (MIMO) is constructed at Lund University. This testbed uses 16-antenna panels as a base for the distributed MIMO system. As the mixers in these panels are fully digital, there is a rational relationship between the sample frequency and the clock frequency of the field-programmable gate-array that performs the digital baseband processing. This rational relationship, combined with the multiple data streams in the panel, makes for an interesting design challenge when implementing high-utilization circuits. Three unique 16 multi-stream fast Fourier transform architectures tailored toward this particular distributed MIMO testbed are presented. The proposed architectures take the rational relationship between clock frequency and sample frequency into consideration and achieve 96.25%–100% butterfly utilization in the multi-streamFFT.

Spade is an HDL that enhances the productivity of HDL designers byadding useful abstractions for hardware design. These abstractionsare zero- or low-cost, meaning that the designer still has full controlover what hardware gets generated.

In this work, we analyze the step-size approximation for fixed-point least-mean-square (LMS) and block LMS (BLMS) algorithms. Our primary focus is on investigating how step size approximation impacts the convergence rate and steady-state mean square error (MSE) across varying block sizes and filter lengths. We consider three different FP quantized LMS and BLMS algorithms. The results demonstrate that the algorithm with two quantizers in single precision behaves approximately the same as one quantizer under quantized weights, regardless of block size and filter lengths. Subsequently, we explore the approximation effects of nearest power-of-two and their combinations with different design parameters on the convergence performance. Simulation results for within the context of a system identification problem under these approximations reveal intriguing insights. For instance, a single quantizer algorithm without quantized error is more robust than its counterpart under these approximations. Additionally, both single quantizer algorithms with combined power-of-two approximations matches the behavior of the actual step-size.

The time-to-market of a new product is one of its most crucial factors for success, therefore, reducing this time is of utter importance. However, this reduction must not come at the expense of a less thorough development process. This paper presents a compiler-driven approach for automatically analyzing metrics such as transaction delays or bus throughput on simulation waveforms of projects developed in the Spade Hardware Description Language (HDL). By utilizing the Spade compiler’s knowledge about design internals, an automatic analysis of the waveforms created during simulation is possible using the Waveform Analysis Language (WAL). Analysis programs can be bundled with Spade projects or libraries, such that they are automatically detected by Spade and can be reused by other projects using simple annotations. We call these bundled WAL programs analysis passes, since they fit into the Spade workflow and provide thorough analysis at no additional cost to the users of these libraries. In a detailed description, we present how new analysis passes can be defined using the example of a data streaming interface. Additionally, we highlight the possibilities of analysis passes in two case studies, including Finite State Machine (FSM) and Wishbone protocol analysis.

FIR filtering realized in frequency domain can use different FFT sizes leading to different arithmetic complexities. The implementation results indicate that not only arithmetic complexities must be considered for minimal power consumption.

Spade is a new open source hardware descriptionlanguage (HDL) designed to increase developer productivitywithout sacrificing the low-level control offered by HDLs. Itis a standalone language which takes inspiration from modernsoftware languages, and adds useful abstractions for commonhardware constructs. It also comes with a convenient set of tool-ing, such as a helpful compiler, a build system with dependencymanagement, tools for debugging, and editor integration.

Matrix transposition, the procedure of swapping rows and columns of a matrix, has applications in various signal processing applications, such as massive multiple-input multiple-output (MIMO) communication systems, data compression, and multidimensional fast Fourier transforms – which are used in MIMO radar systems. In low-latency high-throughput streaming applications, specialized circuits for matrix transposition are needed in order to perform transposition in real-time. This is in contrast to "slower" applications, where transposition can be adequately performed by storing a matrix in a shared memory and afterward reading it back in a transposed order. In this paper, a design procedure for streaming matrix transposition on field-programmable gate arrays (FPGAs) using distributed memories is presented. It is shown that significantly fewer FPGA resources are required for small- to medium-sized streaming matrix transpositions compared to recent related works.

In this work, implementation trade-offs for ASIC-implementation of least-mean-square (LMS) and block LMS (BLMS) adaptive filters are presented. We explore the design trade-offs by increasing the block size and/or relying on the synthesis tool for increased sample rate. For area, lower block size is advantageous as long as the synthesis tool can meet timing. Energy optimum is however found at a different point in design space. Simulation confirms that longer block sizes leads to lower MSE errors for identical step-size. Hence, the design-point should be decided based on weighted requirements for area, energy and MSE.