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Optimal integrated code generation for VLIW architectures
Linköping University, Department of Computer and Information Science, PELAB - Programming Environment Laboratory. Linköping University, The Institute of Technology.
Linköping University, Department of Computer and Information Science, PELAB - Programming Environment Laboratory. Linköping University, The Institute of Technology.ORCID iD: 0000-0001-5241-0026
2003 (English)In: Proc. of CPC'03 10th Int. Workshop on Compilers for Parallel Computers, Amsterdam, The Netherlands, January 2003', Leiden, The Netherlands: Leiden Institute of Advanced Computer Science , 2003Conference paper, Published paper (Refereed)
Place, publisher, year, edition, pages
Leiden, The Netherlands: Leiden Institute of Advanced Computer Science , 2003.
Keywords [en]
code generation, VLIW architecture, Digital signal processor, instruction scheduling, instruction selection, register allocation, dynamic programming
National Category
Engineering and Technology
Identifiers
URN: urn:nbn:se:liu:diva-61612OAI: oai:DiVA.org:liu-61612DiVA, id: diva2:370609
Available from: 2010-11-17 Created: 2010-11-17 Last updated: 2014-10-08

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Bednarski, AndrzejKessler, Christoph

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Total: 233 hits
CiteExportLink to record
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Citation style
  • apa
  • ieee
  • modern-language-association-8th-edition
  • vancouver
  • oxford
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More styles
Language
  • de-DE
  • en-GB
  • en-US
  • fi-FI
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  • nn-NB
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  • Other locale
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Output format
  • html
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  • asciidoc
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