Integrated circuits play a vital role in our everyday lives, from wireless gadgets and multimedia players to sensors and processors that control vital infrastructure. Since most electronic circuits need a clean, stable clock or carrier to function, one of the most important components of integrated circuits is the phase-locked loop. The performance metrics of the phase-locked loop, such as output frequency and range, phase noise, power consumption as well as development and manufacturing costs, all have a great impact on the circuit it serves. Hence, a lot of research has been conducted with the aim to improve its performance. While phase-locked loop performance has increased by orders of magnitude over its 90-year-old history, there is still more to be done. The aim of this thesis is to continue the strive for better performance.

The thesis covers four topics of phase-locked loop design; modeling, calibration, fractional division and the fractional-N sub-sampling phase-locked loop. Apart from the sub-sampling phaselocked loop, only analog Type-II phase-locked loops are considered. The structure of the thesis is as follows. Chapter 2 covers the basics of phase-locked loop theory, such as system metrics, components, dynamics and phase noise. Readers who are familiar with analog phase-locked loops may wish to skip this chapter.

Chapter 3 discusses state-of-the-art phase-locked loop time-domain models. An improved model implementation based on a quantized-state system is introduced with reference to Paper II, where it is shown how this can be implemented in Verilog-AMS. This type of model is ideal for phase-locked loop modeling as it is fully event-based, yet is still able to solve the ordinary differential equations of the loop filter. Improvements on the model presented in Paper II are also discussed.

Chapter 4 looks at phase-locked loop frequency calibration for multi-band voltage-controlled oscillators, as well as gain calibration. A novel method for calibrating both frequency and gain, presented in Paper I, is introduced. This method allows for reduced calibration time without the need to resort to high-speed counters or complex analog circuitry. A simple bang-bang phase detector and a proportional/integral-controller are used to close the calibration loop. Furthermore, the voltage-controlled oscillator tuning voltage is initialized without the use of switches in the loop filter. Further improvements to this method are also presented.

Chapter 5 discusses attempts to suppress sigma-delta noise, and the need for a truly fractional divider. State-of-the-art methods for fractional division are described and discussed. A novel RC-based phase interpolator is introduced with reference to Paper III. This phase interpolator is based on the method of constant-slope charging using current mirrors, but instead uses an inverse exponential charging curve. The phase interpolator unit is built from passive components and switches, which is well suited for nanometer-scale CMOS. The lack of current mirrors also reduces noise. The chapter finishes with presenting measurement results of an improved implementation.

Chapter 6 combines the methods and circuits proposed in Chapters 3-5 to model and analyse a fractional-N sub-sampling phase-locked loop. The phase-locked loop is analysed from a system perspective, proving that the introduction of a divider does not degrade the superior charge pump noise performance often associated with sub-sampling phase-locked loops. Furthermore, an improved differential sampler is presented, with superior power supply rejection ratio. Finally, simulation results for the entire phase-locked loop is presented.