We investigate the use of ring counters as phase accumulator in VCO-based ADCs. An experimental phase accumulator is proposed that consists of parallel ring counters designed with latches. The ring counters count both negative and positive input edges and use special decoding of counter output and feedback to obtain Gray code, facilitating sampling of the outputs. The outputs are combined by selecting sequence lengths that in combination realize a residue number system (RNS), significantly reducing the hardware cost for implementing long sequences that would be very costly to achieve with a single ring counter. We discuss the conversion from the parallel cyclic Johnson code sequences, first to RNS, and then to binary. Area and power requirements are evaluated through design of two 8 bit phase accumulators that are synthesized towards a standard cells implementation in a 65 nm bulk CMOS process. Proposed phase accumulator consumes about 2/3 more area and half the power over a reference implementation designed with reflected binary Gray counters.