liu.seSearch for publications in DiVA
Endre søk
RefereraExporteraLink to record
Permanent link

Direct link
Referera
Referensformat
  • apa
  • ieee
  • modern-language-association-8th-edition
  • vancouver
  • oxford
  • Annet format
Fler format
Språk
  • de-DE
  • en-GB
  • en-US
  • fi-FI
  • nn-NO
  • nn-NB
  • sv-SE
  • Annet språk
Fler språk
Utmatningsformat
  • html
  • text
  • asciidoc
  • rtf
High-Level Programming of FPGA-Accelerated Systems with Parallel Patterns
Linköpings universitet, Institutionen för datavetenskap. Linköpings universitet, Tekniska fakulteten. (PELAB)
Linköpings universitet, Institutionen för datavetenskap, Programvara och system. Linköpings universitet, Tekniska fakulteten. (PELAB)ORCID-id: 0000-0001-6514-4601
Linköpings universitet, Institutionen för datavetenskap, Programvara och system. Linköpings universitet, Tekniska fakulteten. (PELAB)ORCID-id: 0000-0002-7400-4325
Linköpings universitet, Institutionen för datavetenskap, Programvara och system. Linköpings universitet, Tekniska fakulteten. (PELAB)ORCID-id: 0000-0001-5241-0026
2024 (engelsk)Inngår i: International journal of parallel programming, ISSN 0885-7458, E-ISSN 1573-7640, Vol. 52, s. 253-273Artikkel i tidsskrift (Fagfellevurdert) Published
Abstract [en]

As a result of frequency and power limitations, multi-core processors and accelerators are becoming more and more prevalent in today's systems. To fully utilize such systems, heterogeneous parallel programming is needed, but this introduces new complexities to the development. High-level frameworks such as SkePU have been introduced to help alleviate these complexities. SkePU is a skeleton programming framework based on a set of programming constructs implementing computational parallel patterns, while presenting a sequential interface to the programmer. Using the various skeleton backends, SkePU programs can execute, without source code modification, on multiple types of hardware such as CPUs, GPUs, and clusters. This paper presents the design and implementation of a new backend for SkePU, adding support for FPGAs. We also evaluate the effect of FPGA-specific optimizations in the new backend and compare it with the existing GPU backend, where the actual devices used are of similar vintage and price point. For simple examples, we find that the FPGA-backend's performance is similar to that of the existing backend for GPUs, while it falls behind in more complex tasks. Finally, some shortcomings in the backend are highlighted and discussed, along with potential solutions.

sted, utgiver, år, opplag, sider
SPRINGER/PLENUM PUBLISHERS , 2024. Vol. 52, s. 253-273
Emneord [en]
Algorithmic skeletons; Reconfigurable computing; FPGA; Single-source heterogeneous programming
HSV kategori
Identifikatorer
URN: urn:nbn:se:liu:diva-204318DOI: 10.1007/s10766-024-00770-3ISI: 001232114600001Scopus ID: 2-s2.0-85194550594OAI: oai:DiVA.org:liu-204318DiVA, id: diva2:1868160
Merknad

Funding Agencies|Linkping University; ELLIIT; Swedish National Graduate School in Computer Science (CUGS); NSC

Tilgjengelig fra: 2024-06-11 Laget: 2024-06-11 Sist oppdatert: 2025-01-14bibliografisk kontrollert

Open Access i DiVA

Fulltekst mangler i DiVA

Andre lenker

Forlagets fulltekstScopus

Person

Ernstsson, AugustTinnerholm, JohnKessler, Christoph

Søk i DiVA

Av forfatter/redaktør
Birath, BjörnErnstsson, AugustTinnerholm, JohnKessler, Christoph
Av organisasjonen
I samme tidsskrift
International journal of parallel programming

Søk utenfor DiVA

GoogleGoogle Scholar

doi
urn-nbn

Altmetric

doi
urn-nbn
Totalt: 213 treff
RefereraExporteraLink to record
Permanent link

Direct link
Referera
Referensformat
  • apa
  • ieee
  • modern-language-association-8th-edition
  • vancouver
  • oxford
  • Annet format
Fler format
Språk
  • de-DE
  • en-GB
  • en-US
  • fi-FI
  • nn-NO
  • nn-NB
  • sv-SE
  • Annet språk
Fler språk
Utmatningsformat
  • html
  • text
  • asciidoc
  • rtf