In the last decade, the interest for high speed wireless and on cable communication has increased. Orthogonal Frequency Division Multiplexing (OFDM) is a strong candidates and has been suggested or standardized in those communication systems. One key component in OFDM-based systems is FFT processor, which performs the efficient modulation/demodulation.

There are many FFT architectures. Among them, the pipeline architectures are suitable for the real-time communication systems. This thesis presents the implementation of pipeline FFT processors that has low power consumptions.

We select the meet-in-the-middle design methodology for the implementation of FFT processors. A resource analysis for the pipeline architectures is presented. This resource analysis determines the number of memories, butterflies, and complex multipliers to meet the specification.

We present a wordlengths optimization method for the pipeline architectures. We show that the high radix butterfly can be efficiently implemented with carry-save technique, which reduce the hardware complexity and the delay. We present also an efficient implementation of complex multiplier using distributed arithmetic (DA). The implementation of low voltage memories is also discussed.

Finally, we present a 16-point butterfly using constant multipliers that reduces the total number of complex multiplications. The FFT processor using the 16-point butterflies is a competitive candidate for low power applications.