Modern high data rate communication use modulated signals with large peak-to-average power ratios (PAPR). The power efficiency of such signals when using common types of power amplifiers (PAs) can be rather low, as they require a large output back-off (OBO) to be reasonably linear. In this paper, a recent new architecture for improving the efficiency at OBO, the load modulated balanced amplifier (LMBA), is studied by circuit and EM simulations for realization in a 180 nm CMOS process, including matching networks and power combiners (90 degrees couplers). The selected structure is a Doherty-like LMBA, where the control signal for the load modulation is generated by a separate, integrated amplifier. Simulated with on-chip inductor losses and center frequency of 2 GHz, the peak PAE at full output power (24 dBm) is 34.8%. At 6 dB OBO, the LMBA gives a PAE of 32.6% compared to 23.2% for a reference amplifier without load modulation, and load optimized for peak PAE, an absolute PAE improvement of 7.4% or a relative PAE improvement of 31.9%. The main limitation of the integrated CMOS LMBA appears to be losses in the passive components needed for matching and load modulation.