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Wordlength inference in the Spade HDL: Seven implementations of wordlength inference and one implementation that actually works
Linköping University, Department of Electrical Engineering.
2023 (English)Independent thesis Advanced level (degree of Master (Two Years)), 28 HE creditsStudent thesisAlternative title
Ordlängdsinferans i Spade HDL : Sju olika implementationer av ordlängdsinferens och en implementation som faktiskt fungerar (Swedish)
Abstract [en]

Compilers, complex programs with the potential to greatly facilitate software and hardware design. This thesis focuses on enhancing the Spade hardware description language, known for its user-friendly approach to hardware design. In the realm of hardware development data size - for numerical values data size is known as "wordlength" - plays a critical role for reducing the hardware resources. This study presents an innovative approach that seamlessly integrates wordlength inference directly into the Spade language, enabling the over-estimation of numeric data sizes solely from the program's source code.

The methodology involves iterative development, incorporating various smaller implementations and evaluations, reminiscent of an agile approach. To assess the efficacy of the wordlength inference, multiple place and route operations are performed on identical Spade code using various versions of nextpnr. Surprisingly, no discernible impact on hardware resource utilization emerges from the modifications introduced in this thesis.

Nonetheless, the true significance of this endeavor lies in its potential to unlock more advanced language features within the Spade compiler. It is important to note that while the wordlength inference proposed in this thesis shows promise, it necessitates further integration efforts to realize its full potential.

Place, publisher, year, edition, pages
2023. , p. 41
Keywords [en]
FPGA, spade, wordlength inference, word length, word-length, compiler, hdl, hardware description language, LUT, lookup tables, resource usage, compiler
Keywords [sv]
FPGA, spade, ordlängdsinferens, kompilator, hdl, ordlängd
National Category
Computer Engineering Language Technology (Computational Linguistics) Embedded Systems
Identifiers
URN: urn:nbn:se:liu:diva-199193ISRN: LiTH-ISY-EX--23/5624--SEOAI: oai:DiVA.org:liu-199193DiVA, id: diva2:1812391
Subject / course
Computer Engineering
Presentation
2023-11-13, Systemet, Campus Valla, B-huset, Entrance 27, Linköping, 19:44 (Swedish)
Supervisors
Examiners
Available from: 2023-11-20 Created: 2023-11-15 Last updated: 2023-11-20Bibliographically approved

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3031323334353633 of 78
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