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Low-Complexity Memoryless Linearizer for Analog-to-Digital Interfaces
Linköping University, Department of Electrical Engineering, Communication Systems. Linköping University, Faculty of Science & Engineering.ORCID iD: 0009-0004-1846-9496
Linköping University, Department of Electrical Engineering, Communication Systems. Linköping University, Faculty of Science & Engineering.ORCID iD: 0000-0001-6329-9132
2023 (English)In: 2023 24th International Conference on Digital Signal Processing (DSP), Institute of Electrical and Electronics Engineers (IEEE), 2023Conference paper, Published paper (Refereed)
Abstract [en]

This paper introduces a low-complexity memoryless linearizer for suppression of distortion in analog-to-digital interfaces. It is inspired by neural networks, but has a substantially lower complexity than the neural network schemes that have appeared earlier in the literature in this context. The paper demonstrates that the proposed linearizer can outperform the conventional parallel memoryless Hammerstein linearizer even when the nonlinearities have been generated through a memoryless polynomial model. Further, a design procedure is proposed in which the linearizer parameters are obtained through matrix inversion. Thereby, the costly and time consuming it- erative nonconvex optimization that is traditionally used when training neural networks is eliminated. Moreover, the design and evaluation incorporate a large set of multi-tone signals covering the first Nyquist band. Simulations show signal-to-noise-and-distortion ratio (SNDR) improvements of some 25 dB for multi-tone signals that correspond to the quadrature parts of OFDM signals with QPSK modulation.

Place, publisher, year, edition, pages
Institute of Electrical and Electronics Engineers (IEEE), 2023.
Series
International Conference on Digital Signal Processing (DSP), ISSN 1546-1874, E-ISSN 2165-3577
National Category
Signal Processing
Identifiers
URN: urn:nbn:se:liu:diva-201140DOI: 10.1109/DSP58604.2023.10167765Scopus ID: 2-s2.0-85165488092ISBN: 9798350339598 (electronic)ISBN: 9798350339604 (print)OAI: oai:DiVA.org:liu-201140DiVA, id: diva2:1840286
Conference
2023 24th International Conference on Digital Signal Processing (DSP), Rhodes (Rodos), Greece, 11-13 June, 2023.
Funder
ELLIIT - The Linköping‐Lund Initiative on IT and Mobile Communications, B02Available from: 2024-02-23 Created: 2024-02-23 Last updated: 2026-03-19Bibliographically approved
In thesis
1. Contributions to Low-Complexity Linearization, Equalization, and Synchronization
Open this publication in new window or tab >>Contributions to Low-Complexity Linearization, Equalization, and Synchronization
2026 (English)Doctoral thesis, comprehensive summary (Other academic)
Abstract [en]

Analog-to-digital and digital-to-analog interfaces (ADIs and DAIs) constitute the essential link between the analog physical world and digital signal processing systems. As modern communication systems demand higher bandwidths,improved linearity, and increased energy efficiency, imperfections such as linear and nonlinear distortion and sampling errors increasingly limit achievable performance. Such imperfections require compensation techniques that are both effective and computationally efficient for high-speed, high-resolution implementations. This thesis contributes low-complexity solutions for linearization,equalization, and sampling-frequency synchronization, enabling efficient signal processing in high-speed data-conversion systems.

Firstly, the design of low-complexity digital linearizers for ADIs is addressed. Several novel linearizers are introduced that are inspired by neuralnetwork architectures, but avoid the high training complexity associated with neural-network-based approaches. These linearizers can outperform classical linearizers, such as Wiener and Hammerstein, while requiring lower implementation complexity. The proposed designs cover both memoryless and memory (frequency-dependent) linearizers and are applicable to nonlinear distortion occurring either before or after sampling. All designs enable closed-form parameter estimation via matrix inversion, thereby eliminating the need for unpredictable iterative nonconvex optimization. In addition,an efficient memoryless linearizer based on 1-bit quantization is introduced,enabling lookup-table-based implementations with only one multiplication per corrected sample.

Secondly, equalization of digital-to-analog converters (DACs) frequency response using linear-phase finite impulse response (FIR) filters is considered. For several DAC pulse shapes operating across multiple Nyquist bands,minimax-optimal equalizers are designed, and their properties are analyzed. Based on these designs, expressions for the required filter order are derived as explicit functions of bandwidth and target equalization accuracy, using symbolic regression followed by further refinement. The resulting expressions provide accurate order estimates across different pulse shapes and operating conditions.

Thirdly, a low-complexity time-domain sampling frequency offset (SFO)estimation and compensation framework based on the Farrow structure for interpolation is presented. By reusing the Farrow structure already employed for SFO compensation, the proposed approach enables a unified estimation and compensation architecture with significantly reduced overall implementation complexity. The method operates on arbitrary bandlimited signals, supports joint estimation of SFO and sampling time offset, and allows estimation using only a single component (real or imaginary) of a complex signal. A Newton-based estimator exploiting the structure of the problem is developed to reduce computational complexity, while an alternative iterative least-squares-based design provides an even lower-complexity solution. The resulting estimators are robust to other synchronization errors and are well suited for practical receiver implementations. In addition, motivated by the appearance of low-order time-index-powered sums in the Farrow-based formulation, a general cascaded-accumulator framework is developed as a supplementary contribution, enabling efficient causal computation of time-index-powered weighted sums of arbitrary order without data buffering and reducing the multiplicative complexity from order K N to only K+1 constant multiplications (where N is the number of terms and K is the power in the sum), which is applicable both to SFO estimators and to other signal processing applications beyond the SFO problem.

Place, publisher, year, edition, pages
Linköping: Linköping University Electronic Press, 2026. p. 60
Series
Linköping Studies in Science and Technology. Dissertations, ISSN 0345-7524 ; 2514
National Category
Signal Processing Communication Systems
Identifiers
urn:nbn:se:liu:diva-222071 (URN)10.3384/9789181185065 (DOI)9789181185058 (ISBN)9789181185065 (ISBN)
Public defence
2026-04-17, Ada Lovelace, B-Huset, Campus Valla, Linköping, 09:00 (English)
Opponent
Supervisors
Available from: 2026-03-19 Created: 2026-03-19Bibliographically approved

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Rodríguez Linares, DeijanyJohansson, Håkan

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