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Scalable FPGA Implementation of Dynamic Programming for Optimal Control of Hybrid Electrical Vehicles
Linköping University, Department of Electrical Engineering, Computer Engineering. Linköping University, Faculty of Science & Engineering.ORCID iD: 0000-0001-7089-9697
Linköping University, Department of Electrical Engineering, Computer Engineering. Linköping University, Faculty of Science & Engineering.ORCID iD: 0000-0003-3470-3911
2024 (English)In: DESIGN AND ARCHITECTURES FOR SIGNAL AND IMAGE PROCESSING, DASIP 2024, SPRINGER INTERNATIONAL PUBLISHING AG , 2024, Vol. 14622, p. 27-39Conference paper, Published paper (Refereed)
Abstract [en]

Dynamic programming (DP) can be used for optimal control of hybrid electric vehicles but requires a large number of computations to be performed. As many of these computations can be performed in parallel, FPGAs are an interesting platform for executing the dynamic programming algorithm. This paper presents a scalable architecture for performing dynamic programming on FPGAs using a pipelined model of a hybrid electric vehicle (HEV). The proposed architecture supports multiple parallel model execution units and is scalable to support a configurable number of units, inputs, states, and time steps. The run time of the optimization process is shown to be improved significantly compared to a CPU implementation. With four parallel model execution units, the design runs in about 1.5% of the time required for an Intel Xeon W-1250 CPU. This shows that DP-based optimal control is feasible for HEVs and that FPGAs can be used to achieve it.

Place, publisher, year, edition, pages
SPRINGER INTERNATIONAL PUBLISHING AG , 2024. Vol. 14622, p. 27-39
Series
Lecture Notes in Computer Science, ISSN 0302-9743
National Category
Embedded Systems
Identifiers
URN: urn:nbn:se:liu:diva-207490DOI: 10.1007/978-3-031-62874-0_3ISI: 001283306100003ISBN: 9783031628733 (print)ISBN: 9783031628740 (electronic)OAI: oai:DiVA.org:liu-207490DiVA, id: diva2:1896541
Conference
17th International Workshop on Design and Architecture for Signal and Image Processing (DASIP), Munich, GERMANY, jan 17-19, 2024
Available from: 2024-09-10 Created: 2024-09-10 Last updated: 2025-06-03
In thesis
1. Improved Tooling for Digital Hardware Development: Spade, Surfer, and more
Open this publication in new window or tab >>Improved Tooling for Digital Hardware Development: Spade, Surfer, and more
2025 (English)Doctoral thesis, comprehensive summary (Other academic)
Abstract [en]

Hardware complexity is ever-growing but the front-end tools used to design hardware are not keeping up, especially when compared with software tooling. While software and hardware have fundamental differences, there is enough overlap between the domains to warrant taking ideas and inspiration from software tooling to build better hardware tooling. This dissertation is made up of three parts, each focused around a tool that was built in part based on this idea.

The first tool is Spade, a hardware description language built with the explicit goal of improving developer productivity by taking inspiration from software programming languages. Some features are carried over outright: the type system, a build system with easy dependency management, and a compiler that produces helpful error messages. Most features however, are built specifically for hardware based on design philosophy from software, these include an abstraction for correct by construction pipelining, linear types for modeling memory ports, and the ability to define new custom hardware-centric abstractions such as ready valid interfaces.

The second tool is Surfer, a waveform viewer built from the ground up to accommodate new hardware design workflows. One example of this is integration with modern HDLs like Spade to allow full use of their complex type systems. Other examples include the ability to embed the waveform viewer in bigger project, to control it externally, and to use it in web technologies. The viewer has already seen widespread adoption, has integration with Chisel, Clash, and RHDL in addition to Spade, and is used as a component of several proprietary and open source tools.

The final part of the thesis is centered around Cinnabar, a new high level synthesis tool. It lays the groundwork for a way for domain experts to work with hardware engineers to build accelerators for model based control applications. To do this efficiently, it is helpful if the domain experts can work on the modeling largely independently of the hardware engineers working on the hardware architecture. This is achieved by a high level synthesis tool that compiles a simulation model to efficient hardware without requiring any domain expertise. In parallel, a hardware engineer can develop the hardware which executes the simulation, a task which requires less domain expertise and where high level synthesis typically performs worse than a handwritten solution.

In order to tie these works together, a simulation model of a hybrid electric vehicle synthesized with high level synthesis was combined with hardware written in Spade for performing dynamic programming. Together, this allows real time use of an algorithm for optimizing fuel efficiency, which has traditionally only been possible off-line when executing on CPUs.

Place, publisher, year, edition, pages
Linköping: Linköping University Electronic Press, 2025. p. 55
Series
Linköping Studies in Science and Technology. Dissertations, ISSN 0345-7524 ; 2460
National Category
Embedded Systems
Identifiers
urn:nbn:se:liu:diva-214272 (URN)10.3384/9789181181777 (DOI)9789181181760 (ISBN)9789181181777 (ISBN)
Public defence
2025-08-29, Planck, F-building, Campus Valla, Linköping, 09:15 (English)
Opponent
Supervisors
Available from: 2025-06-03 Created: 2025-06-03 Last updated: 2025-06-03Bibliographically approved

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