The time-to-market of a new product is one of its most crucial factors for success, therefore, reducing this time is of utter importance. However, this reduction must not come at the expense of a less thorough development process. This paper presents a compiler-driven approach for automatically analyzing metrics such as transaction delays or bus throughput on simulation waveforms of projects developed in the Spade Hardware Description Language (HDL). By utilizing the Spade compiler’s knowledge about design internals, an automatic analysis of the waveforms created during simulation is possible using the Waveform Analysis Language (WAL). Analysis programs can be bundled with Spade projects or libraries, such that they are automatically detected by Spade and can be reused by other projects using simple annotations. We call these bundled WAL programs analysis passes, since they fit into the Spade workflow and provide thorough analysis at no additional cost to the users of these libraries. In a detailed description, we present how new analysis passes can be defined using the example of a data streaming interface. Additionally, we highlight the possibilities of analysis passes in two case studies, including Finite State Machine (FSM) and Wishbone protocol analysis.

When optimising the vehicle trajectory and powertrain energy management of hybrid electric vehicles, it is important to include look-ahead information such as road conditions and other traffic. One method for doing so is dynamic programming, but the execution time of such an algorithm on a general purpose CPU is too slow for it to be useable in real time. Significant improvements in execution time can be achieved by utilising parallel computations, for example, using a Field-Programmable Gate Array (FPGA). A tool for automatically converting a vehicle model written in C++ into code that can executed on an FPGA which can be used for dynamic programming-based control is presented in this paper. A vehicle model with a mild-hybrid powertrain is used as a case study to evaluate the developed tool and the output quality and execution time of the resulting hardware. Copyright (C) 2020 The Authors.

Dynamic programming (DP) can be used for optimal control of hybrid electric vehicles but requires a large number of computations to be performed. As many of these computations can be performed in parallel, FPGAs are an interesting platform for executing the dynamic programming algorithm. This paper presents a scalable architecture for performing dynamic programming on FPGAs using a pipelined model of a hybrid electric vehicle (HEV). The proposed architecture supports multiple parallel model execution units and is scalable to support a configurable number of units, inputs, states, and time steps. The run time of the optimization process is shown to be improved significantly compared to a CPU implementation. With four parallel model execution units, the design runs in about 1.5% of the time required for an Intel Xeon W-1250 CPU. This shows that DP-based optimal control is feasible for HEVs and that FPGAs can be used to achieve it.