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Joint Sampling Frequency Offset Estimation and Compensation Based on the Farrow Structure
Linköping University, Department of Electrical Engineering, Communication Systems. Linköping University, Faculty of Science & Engineering.ORCID iD: 0009-0004-1846-9496
Linköping University, Department of Electrical Engineering, Communication Systems. Linköping University, Faculty of Science & Engineering.
Linköping University, Department of Electrical Engineering, Communication Systems. Linköping University, Faculty of Science & Engineering.ORCID iD: 0000-0001-6329-9132
2025 (English)In: 2025 25TH INTERNATIONAL CONFERENCE ON DIGITAL SIGNAL PROCESSING, DSP, IEEE , 2025Conference paper, Published paper (Refereed)
Abstract [en]

This paper introduces a sampling frequency offset (SFO) estimation method based on the Farrow structure, which is typically utilized for the SFO compensation and thereby enables a reduction of the implementation complexity of the SFO estimation. The proposed method is implemented in the time domain and works for arbitrary bandlimited signals, thus with no additional constraints on the waveform structure. Moreover, it can operate on only the real or imaginary part of a complex signal, which further reduces the estimation complexity. Furthermore, the proposed method can simultaneously estimate the SFO and additional sampling time offset (STO) and it is insensitive to other synchronization errors, like carrier frequency offset. Both the derivations of the proposed method and its implementation are presented, and through simulation examples, it is demonstrated that it can accurately estimate both SFO and STO for different types of bandlimited signals.

Place, publisher, year, edition, pages
IEEE , 2025.
Series
International Conference on Digital Signal Processing, ISSN 1546-1874, E-ISSN 2165-3577
National Category
Signal Processing
Identifiers
URN: urn:nbn:se:liu:diva-219094DOI: 10.1109/DSP65409.2025.11074995ISI: 001556221900046Scopus ID: 2-s2.0-105012180434ISBN: 9798331512149 (print)ISBN: 9798331512132 (electronic)OAI: oai:DiVA.org:liu-219094DiVA, id: diva2:2009832
Conference
9th International Conference on Digital Signal Processing-ICDSP, Chengdu, PEOPLES R CHINA, feb 21-23, 2025
Note

Funding Agencies|ELLIIT and Sweden's Innovation Agency

Available from: 2025-10-29 Created: 2025-10-29 Last updated: 2026-04-02
In thesis
1. Contributions to Low-Complexity Linearization, Equalization, and Synchronization
Open this publication in new window or tab >>Contributions to Low-Complexity Linearization, Equalization, and Synchronization
2026 (English)Doctoral thesis, comprehensive summary (Other academic)
Abstract [en]

Analog-to-digital and digital-to-analog interfaces (ADIs and DAIs) constitute the essential link between the analog physical world and digital signal processing systems. As modern communication systems demand higher bandwidths,improved linearity, and increased energy efficiency, imperfections such as linear and nonlinear distortion and sampling errors increasingly limit achievable performance. Such imperfections require compensation techniques that are both effective and computationally efficient for high-speed, high-resolution implementations. This thesis contributes low-complexity solutions for linearization,equalization, and sampling-frequency synchronization, enabling efficient signal processing in high-speed data-conversion systems.

Firstly, the design of low-complexity digital linearizers for ADIs is addressed. Several novel linearizers are introduced that are inspired by neuralnetwork architectures, but avoid the high training complexity associated with neural-network-based approaches. These linearizers can outperform classical linearizers, such as Wiener and Hammerstein, while requiring lower implementation complexity. The proposed designs cover both memoryless and memory (frequency-dependent) linearizers and are applicable to nonlinear distortion occurring either before or after sampling. All designs enable closed-form parameter estimation via matrix inversion, thereby eliminating the need for unpredictable iterative nonconvex optimization. In addition,an efficient memoryless linearizer based on 1-bit quantization is introduced,enabling lookup-table-based implementations with only one multiplication per corrected sample.

Secondly, equalization of digital-to-analog converters (DACs) frequency response using linear-phase finite impulse response (FIR) filters is considered. For several DAC pulse shapes operating across multiple Nyquist bands,minimax-optimal equalizers are designed, and their properties are analyzed. Based on these designs, expressions for the required filter order are derived as explicit functions of bandwidth and target equalization accuracy, using symbolic regression followed by further refinement. The resulting expressions provide accurate order estimates across different pulse shapes and operating conditions.

Thirdly, a low-complexity time-domain sampling frequency offset (SFO)estimation and compensation framework based on the Farrow structure for interpolation is presented. By reusing the Farrow structure already employed for SFO compensation, the proposed approach enables a unified estimation and compensation architecture with significantly reduced overall implementation complexity. The method operates on arbitrary bandlimited signals, supports joint estimation of SFO and sampling time offset, and allows estimation using only a single component (real or imaginary) of a complex signal. A Newton-based estimator exploiting the structure of the problem is developed to reduce computational complexity, while an alternative iterative least-squares-based design provides an even lower-complexity solution. The resulting estimators are robust to other synchronization errors and are well suited for practical receiver implementations. In addition, motivated by the appearance of low-order time-index-powered sums in the Farrow-based formulation, a general cascaded-accumulator framework is developed as a supplementary contribution, enabling efficient causal computation of time-index-powered weighted sums of arbitrary order without data buffering and reducing the multiplicative complexity from order K N to only K+1 constant multiplications (where N is the number of terms and K is the power in the sum), which is applicable both to SFO estimators and to other signal processing applications beyond the SFO problem.

Place, publisher, year, edition, pages
Linköping: Linköping University Electronic Press, 2026. p. 60
Series
Linköping Studies in Science and Technology. Dissertations, ISSN 0345-7524 ; 2514
National Category
Signal Processing Communication Systems
Identifiers
urn:nbn:se:liu:diva-222071 (URN)10.3384/9789181185065 (DOI)9789181185058 (ISBN)9789181185065 (ISBN)
Public defence
2026-04-17, Ada Lovelace, B-Huset, Campus Valla, Linköping, 09:00 (English)
Opponent
Supervisors
Available from: 2026-03-19 Created: 2026-03-19Bibliographically approved
2. Efficient Signal Processing Algorithms for Reconfigurable Digital Filtering, Synchronization, and Power Amplifier Linearization
Open this publication in new window or tab >>Efficient Signal Processing Algorithms for Reconfigurable Digital Filtering, Synchronization, and Power Amplifier Linearization
2026 (English)Doctoral thesis, comprehensive summary (Other academic)
Abstract [en]

Complexity reduction and reconfigurability are challenges in the design of modern communication system front-ends. Each new generation of communication standards brings more stringent requirements on data rates, bandwidth, synchronization, and spectral efficiency, which in turn can lead to increased power consumption and chip area. To meet these requirements and at the same time prevent a rapid growth in power consumption and silicon area, it is necessary to develop more sophisticated digital signal processing (DSP) algorithms that simultaneously can achieve high performance, flexibility, and low implementation cost, particularly in hardware-constrained receiver and transmitter front-ends. This thesis investigates efficient signal processing techniques for reconfigurable communication system front-ends and presents contributions in three directions: design and implementation of variable digital filters (VDFs), efficient synchronization techniques, particularly sampling frequency offset (SFO) estimation and compensation using VDFs, and analysis and optimization of cascaded power amplifiers (PAs), specifically their accumulated nonlinearities.

Since digital filters form the core of DSP algorithms, a key candidate for efficient reconfigurability in digital front-ends is the class of VDFs, which are capable of real-time frequency response tuning without the need for online filter design. The main advantage of VDFs is that they require only an adjustment of one or a few parameters to change their characteristics, while the majority of filter coefficients remain fixed after the initial design. This property eliminates the need for extensive online computations and makes VDFs particularly attractive for modern adaptive communication technologies, enabling efficient hardware implementation. In this area, various aspects of design and implementation of VDFs are presented in the thesis, including: (i) implementations and systematic design procedures based on minimax optimization for reconfigurable finite-impulse-response (FIR) filters for simultaneous equalization and lowpass filtering; (ii) an analysis of chip area and power consumption for application-specific integrated circuit (ASIC) implementation of the reconfigurable lowpass equalizer with simultaneously variable bandwidth; (iii) low-complexity frequency-domain implementations of VDFs based on the assumption that these filters have been designed using a common time-domain design approach based on optimizing the impulse response coefficients; (iv) efficient frequency-sampling-based design approaches (minimax based and closed-form least-squares) for a variablebandwidth FIR filter implemented in the frequency domain, allowing for direct optimization of the DFT coefficients considering the filter frequency-domain implementation and thereby resulting in a substantial reduction in implementation complexity.

Further, accurate synchronization is essential for reliable operation of communication systems, as synchronization errors can significantly degrade overall system performance. Among these impairments, SFO is critical, especially in modern wideband and high-speed communication systems, where even tiny differences between sampling clocks lead to a noticeable cumulative timing drift, resulting in inter-carrier and inter-symbol interference. While the SFO compensation is commonly carried out in the time domain, most existing SFO estimation methods are formulated in the frequency domain, which are generally quite computationally demanding, and it results in a separation between estimation and compensation stages. In contrast to these traditional approaches, this thesis presents two contributions in this area, specifically: (i) a joint SFO estimation and compensation framework based on a variable-fractional- delay filter, that results in reduced implementation complexity of the SFO estimation and is applicable to arbitrary bandlimited signals; (ii) a generalized accumulator-based approach for efficient computation of time-index powered weighted sums, which is employed in the proposed SFO estimation algorithms to implement computation of time-index and time-index-squared weighted sums in an efficient way leading to eliminating considerable parts of multiplications.

Finally, recent advances in wireless communication systems have shown the need for a reconfigurable number of cascaded power amplifiers (PAs). While PAs generally constitute one of the main sources of nonlinearities in a transceiver that distort the transmitted signal and degrade the overall system performance, in cascaded PAs, the distortions from each amplifier accumulate with those from the preceding stages, leading to severe nonlinear behavior. Considering the requirements on high efficiency and a maximally linear operation regime, this thesis investigates the effect of total nonlinearities occurring in cascaded PAs by providing results on modeling, analysis, linearization, and optimization of cascaded amplifiers.

Abstract [sv]

Komplexitetsreduktion och avstämbarhet är utmaningar i konstruktion av moderna kommunikationssystems så kallade front-ends. Varje ny generation av kommunikationsstandard medför strängare krav på datahastigheter, bandbredd, synkronisering och spektral effektivitet, vilket i sin tur kan leda till ökad strömförbrukning och chiparea i en hårdvaruimplementering. För att möta dessa krav och samtidigt förhindra ökning av strömförbrukning och kiselarea är det nödvändigt att utveckla mer sofistikerade algoritmer för digital signalbehandling (DSB) som samtidigt kan uppnå en hög prestanda, flexibilitet och låg implementeringskostnad, särskilt i hårdvarubegränsade mottagar- och sändar-front-ends. Denna avhandling studerar effektiva signalbehandlingstekniker och presenterar tre olika bidrag: konstruktion och implementering av avstämbara digitala filter (VDF), effektiva synkroniseringstekniker, särskilt estimering och kompensation av samplingsfrekvensoffset (SFO) med hjälp av VDF, och analys och optimering av kaskadkopplade effektförstärkare (så kallade PA), särskilt deras ackumulerade olinjäriteter.

Eftersom digitala filter utgör kärnan i DSB-algoritmer är en nyckelkandidat för effektiv avstämbarhet i digitala front-ends klassen av VDF:er som kan finjustera frekvenskarakteristiken i realtid utan behov av onlinefilterdesign. Den största fördelen med VDF:er är att de endast kräver en justering av en eller några få parametrar för att ändra sina egenskaper, medan majoriteten av filterkoefficienterna förblir fixa efter den initiala designen. Denna egenskap eliminerar behovet av omfattande online-beräkningar och gör VDF:er särskilt attraktiva för moderna adaptiva kommunikationstekniker, vilket möjliggör effektiv hårdvaruimplementering. Inom detta område presenterar avhandlingen tre olika tekniker för design och implementering av VDF: (i) implementeringar och systematiska designprocedurer baserade på minimaxoptimering för avstämbara så kallade FIR-filter för samtidig frekvensgångsutjämning och lågpassfiltrering; (ii) implementering av den avstämbara lågpassutjämnaren med samtidigt variabel bandbredd, inklusive analys av chiparea och effektförbrukning i applikationsspecifika integrerade kretsar; (iii) effektiva frekvensdomän-implementeringar av VDF:er som konstruerats via filterdesign i tidsdomänen; (iv) effektiva frekvenssamplingsbaserade designmetoder (minimax och minstakvadrat) för FIR-filter med avstämbar bandbredd implementerat i frekvensdomänen, vilket möjliggör direkt optimering av DFT-koefficienterna med hänsyn till filtrets frekvensdomänimplementering och därigenom resulterar i en signifikant minskning av implementeringskomplexiteten.

Vidare är noggrann synkronisering avgörande för tillförlitlig drift av kommunikationssystem, eftersom synkroniseringsfel kan försämra systemets totala prestanda avsevärt. Bland dessa försämringar är SFO kritisk, särskilt i moderna bredbandiga och höghastighetskommunikationssystem, där även små skillnader mellan samplingsklockor leder till en märkbar kumulativ tidsdrift, vilket resulterar i interferens mellan bärvågor och symboler. Medan SFO-kompensationen vanligtvis utförs i tidsdomänen är de flesta befintliga SFO-estimeringsmetoder formulerade i frekvensdomänen, vilka i allmänhet är ganska beräkningskrävande, och det resulterar i en separation mellan estimering och kompensation. I motsats till dessa traditionella metoder presenterar denna avhandling två bidrag inom detta område: (i) ett gemensamt ramverk för SFO-estimering och kompensation baserat på ett avstämbart fördröjningsfilter, vilket resulterar i minskad implementeringskomplexitet för SFO-estimeringen och är tillämpbart på godtyckliga bandbegränsade signaler; (ii) en generaliserad ackumulatorbaserad metod för effektiv beräkning av viktade summor, som används i de föreslagna SFO-estimeringsalgoritmerna för att implementera beräkning av tidsindex-viktade och tidsindexkvadratviktade summor på ett effektivt sätt, vilket leder till att de flesta av multiplikationerna elimineras.

Slutligen har nya framsteg inom trådlösa kommunikationssystem visat behovet av ett avstämbart antal kaskadkopplade PA-steg. Medan en PA i allmänhet är en av de huvudsakliga källorna till olinjäriteter i en sändarmottagare som förvränger den sända signalen och försämrar systemets totala prestanda, ackumuleras felen i kaskadkopplade PA-steg, vilket leder till större olinjäriteter. Med hänsyn till kraven på hög effektivitet och ett maximalt linjärt driftsområde studerar denna avhandling effekten av totala olinjäriteter som uppstår i kaskadkopplade PA-steg genom modellering, analys, linjärisering och optimering.

Place, publisher, year, edition, pages
Linköping: Linköping University Electronic Press, 2026. p. 87
Series
Linköping Studies in Science and Technology. Dissertations, ISSN 0345-7524 ; 2517
National Category
Communication Systems
Identifiers
urn:nbn:se:liu:diva-222441 (URN)10.3384/9789181185379 (DOI)9789181185362 (ISBN)9789181185379 (ISBN)
Public defence
2026-05-13, Ada Lovelace, B Building, Campus Valla, Linköping, 09:00 (English)
Opponent
Supervisors
Note

2026:04-02: The thesis was first published online. The online published version reflects the printed version. 

2026:04-07: The thesis was updated with a new front cover. Before this date the PDF has been downloaded 33 times.

Available from: 2026-04-02 Created: 2026-04-02 Last updated: 2026-04-07Bibliographically approved

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