This thesis details the full process of producing a system in the form of a dataflow accelerator on an FPGA that performs modulation classification. Some background on the four areas: dataset generation, quantization in the context of machine learning, and hardware acceleration of algorithms, along with some introductory information about the framework FINN, is provided. The implementation process is described, and the findings show that, with synthetic data, machine learning models can be trained with quantization-aware training to produce a classification of the modulation type with acceptable accuracy. Hardware can be constructed to run such models on an FPGA, with low power consumption on consumer-grade devices, with sufficient performance to be usable for practical applications. There are limitations and considerations that need to be made when constructing such a system, and the design of both hardware and model jointly is critical for success.