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Contributions to Low-Complexity Linearization, Equalization, and Synchronization
Linköping University, Department of Electrical Engineering, Communication Systems. Linköping University, Faculty of Science & Engineering.ORCID iD: 0009-0004-1846-9496
2026 (English)Doctoral thesis, comprehensive summary (Other academic)
Abstract [en]

Analog-to-digital and digital-to-analog interfaces (ADIs and DAIs) constitute the essential link between the analog physical world and digital signal processing systems. As modern communication systems demand higher bandwidths,improved linearity, and increased energy efficiency, imperfections such as linear and nonlinear distortion and sampling errors increasingly limit achievable performance. Such imperfections require compensation techniques that are both effective and computationally efficient for high-speed, high-resolution implementations. This thesis contributes low-complexity solutions for linearization,equalization, and sampling-frequency synchronization, enabling efficient signal processing in high-speed data-conversion systems.

Firstly, the design of low-complexity digital linearizers for ADIs is addressed. Several novel linearizers are introduced that are inspired by neuralnetwork architectures, but avoid the high training complexity associated with neural-network-based approaches. These linearizers can outperform classical linearizers, such as Wiener and Hammerstein, while requiring lower implementation complexity. The proposed designs cover both memoryless and memory (frequency-dependent) linearizers and are applicable to nonlinear distortion occurring either before or after sampling. All designs enable closed-form parameter estimation via matrix inversion, thereby eliminating the need for unpredictable iterative nonconvex optimization. In addition,an efficient memoryless linearizer based on 1-bit quantization is introduced,enabling lookup-table-based implementations with only one multiplication per corrected sample.

Secondly, equalization of digital-to-analog converters (DACs) frequency response using linear-phase finite impulse response (FIR) filters is considered. For several DAC pulse shapes operating across multiple Nyquist bands,minimax-optimal equalizers are designed, and their properties are analyzed. Based on these designs, expressions for the required filter order are derived as explicit functions of bandwidth and target equalization accuracy, using symbolic regression followed by further refinement. The resulting expressions provide accurate order estimates across different pulse shapes and operating conditions.

Thirdly, a low-complexity time-domain sampling frequency offset (SFO)estimation and compensation framework based on the Farrow structure for interpolation is presented. By reusing the Farrow structure already employed for SFO compensation, the proposed approach enables a unified estimation and compensation architecture with significantly reduced overall implementation complexity. The method operates on arbitrary bandlimited signals, supports joint estimation of SFO and sampling time offset, and allows estimation using only a single component (real or imaginary) of a complex signal. A Newton-based estimator exploiting the structure of the problem is developed to reduce computational complexity, while an alternative iterative least-squares-based design provides an even lower-complexity solution. The resulting estimators are robust to other synchronization errors and are well suited for practical receiver implementations. In addition, motivated by the appearance of low-order time-index-powered sums in the Farrow-based formulation, a general cascaded-accumulator framework is developed as a supplementary contribution, enabling efficient causal computation of time-index-powered weighted sums of arbitrary order without data buffering and reducing the multiplicative complexity from order K N to only K+1 constant multiplications (where N is the number of terms and K is the power in the sum), which is applicable both to SFO estimators and to other signal processing applications beyond the SFO problem.

Place, publisher, year, edition, pages
Linköping: Linköping University Electronic Press, 2026. , p. 60
Series
Linköping Studies in Science and Technology. Dissertations, ISSN 0345-7524 ; 2514
National Category
Signal Processing Communication Systems
Identifiers
URN: urn:nbn:se:liu:diva-222071DOI: 10.3384/9789181185065ISBN: 9789181185058 (print)ISBN: 9789181185065 (electronic)OAI: oai:DiVA.org:liu-222071DiVA, id: diva2:2047290
Public defence
2026-04-17, Ada Lovelace, B-Huset, Campus Valla, Linköping, 09:00 (English)
Opponent
Supervisors
Available from: 2026-03-19 Created: 2026-03-19Bibliographically approved
List of papers
1. Low-Complexity Memoryless Linearizer for Analog-to-Digital Interfaces
Open this publication in new window or tab >>Low-Complexity Memoryless Linearizer for Analog-to-Digital Interfaces
2023 (English)In: 2023 24th International Conference on Digital Signal Processing (DSP), Institute of Electrical and Electronics Engineers (IEEE), 2023Conference paper, Published paper (Refereed)
Abstract [en]

This paper introduces a low-complexity memoryless linearizer for suppression of distortion in analog-to-digital interfaces. It is inspired by neural networks, but has a substantially lower complexity than the neural network schemes that have appeared earlier in the literature in this context. The paper demonstrates that the proposed linearizer can outperform the conventional parallel memoryless Hammerstein linearizer even when the nonlinearities have been generated through a memoryless polynomial model. Further, a design procedure is proposed in which the linearizer parameters are obtained through matrix inversion. Thereby, the costly and time consuming it- erative nonconvex optimization that is traditionally used when training neural networks is eliminated. Moreover, the design and evaluation incorporate a large set of multi-tone signals covering the first Nyquist band. Simulations show signal-to-noise-and-distortion ratio (SNDR) improvements of some 25 dB for multi-tone signals that correspond to the quadrature parts of OFDM signals with QPSK modulation.

Place, publisher, year, edition, pages
Institute of Electrical and Electronics Engineers (IEEE), 2023
Series
International Conference on Digital Signal Processing (DSP), ISSN 1546-1874, E-ISSN 2165-3577
National Category
Signal Processing
Identifiers
urn:nbn:se:liu:diva-201140 (URN)10.1109/DSP58604.2023.10167765 (DOI)2-s2.0-85165488092 (Scopus ID)9798350339598 (ISBN)9798350339604 (ISBN)
Conference
2023 24th International Conference on Digital Signal Processing (DSP), Rhodes (Rodos), Greece, 11-13 June, 2023.
Funder
ELLIIT - The Linköping‐Lund Initiative on IT and Mobile Communications, B02
Available from: 2024-02-23 Created: 2024-02-23 Last updated: 2026-03-19Bibliographically approved
2. Low-Complexity Frequency-Dependent Linearizers Based on Parallel Bias-Modulus and Bias-ReLU Operations
Open this publication in new window or tab >>Low-Complexity Frequency-Dependent Linearizers Based on Parallel Bias-Modulus and Bias-ReLU Operations
2025 (English)In: IEEE Access, E-ISSN 2169-3536, Vol. 13, p. 209796-209812Article in journal (Refereed) Published
Abstract [en]

This paper introduces low-complexity frequency-dependent (memory) linearizers designed to suppress nonlinear distortion in analog-to-digital interfaces. Two different linearizers are considered, based on nonlinearity models which correspond to sampling before and after the nonlinearity operations, respectively. The proposed linearizers are inspired by convolutional neural networks but have an order-of-magnitude lower implementation complexity compared to existing neural-network-based linearizer schemes. The proposed linearizers can also outperform the traditional parallel Hammerstein linearizers even when the nonlinearities have been generated through a Hammerstein model. Further, a design procedure is proposed in which the linearizer parameters are obtained through matrix inversion. This eliminates the need for costly and time-consuming iterative nonconvex optimization that is traditionally associated with neural network training. The design effectively handles a wide range of wideband multi-tone signals and filtered white noise. Examples demonstrate significant signal-to-noise-and-distortion ratio (SNDR) improvements of about 20–30 dB, as well as a lower implementation complexity than the Hammerstein linearizers.

Place, publisher, year, edition, pages
Institute of Electrical and Electronics Engineers (IEEE), 2025
Keywords
Analog-to-digital interfaces, nonlinear distortion, linearization, frequency-dependent nonlinear systems, pre-sampling, post-sampling
National Category
Signal Processing
Identifiers
urn:nbn:se:liu:diva-220209 (URN)10.1109/access.2025.3642613 (DOI)001641538900020 ()2-s2.0-105024724720 (Scopus ID)
Projects
Baseband Processing for Beyond 5G Wireless, funded by ELLIIT.
Note

Funding Agencies|Project ''Baseband Processing for Beyond 5G Wireless" - ELLIIT

Available from: 2025-12-23 Created: 2025-12-23 Last updated: 2026-03-19
3. Digital Linearizer Based on 1-Bit Quantizations
Open this publication in new window or tab >>Digital Linearizer Based on 1-Bit Quantizations
2024 (English)In: 2024 IEEE 24th International Conference on Communication Technology (ICCT), Institute of Electrical and Electronics Engineers (IEEE) , 2024, p. 1659-1663Conference paper, Published paper (Refereed)
Abstract [en]

This paper introduces a novel low-complexity memoryless linearizer for suppression of distortion in analog frontends. It is based on our recently introduced linearizer which is inspired by neural networks, but with orders-of-magnitude lower complexity than conventional neural-networks considered in this context, and it can also outperform the conventional parallel memoryless Hammerstein linearizer. Further, it can be designed through matrix inversion and thereby the costly and time consuming numerical optimization traditionally used when training neural networks is avoided. The linearizer proposed in this paper is different in that it uses 1-bit quantizations as nonlinear activation functions and different bias values. These features enable a look-up table implementation which eliminates all but one of the multiplications and additions required for the linearization. Extensive simulations and comparisons are included in the paper, for distorted multi-tone signals and bandpass filtered white noise, which demonstrate the efficacy of the proposed linearizer.

Place, publisher, year, edition, pages
Institute of Electrical and Electronics Engineers (IEEE), 2024
Series
International Conference on Communication Technology (ICCT), ISSN 2576-7844, E-ISSN 2576-7828
Keywords
Training;Band-pass filters;Quantization (signal);Costs;Nonlinear distortion;Neural networks;White noise;Table lookup;Computational complexity;Optimization;Analog-to-digital interfaces;nonlinear distortion;memoryless linearizer;1-bit quantization
National Category
Signal Processing
Identifiers
urn:nbn:se:liu:diva-213843 (URN)10.1109/ICCT62411.2024.10946352 (DOI)2-s2.0-105003156925 (Scopus ID)9798350363760 (ISBN)9798350363777 (ISBN)
Conference
International Conference on Communication Technology (ICCT), Chengdu, China, 18-20 October 2024
Projects
ELLIIT
Funder
ELLIIT - The Linköping‐Lund Initiative on IT and Mobile Communications, B02
Available from: 2025-05-26 Created: 2025-05-26 Last updated: 2026-03-19Bibliographically approved
4. Order Estimation of Linear-Phase FIR Filters for DAC Equalization in Multiple Nyquist Bands
Open this publication in new window or tab >>Order Estimation of Linear-Phase FIR Filters for DAC Equalization in Multiple Nyquist Bands
2024 (English)In: IEEE Signal Processing Letters, ISSN 1070-9908, E-ISSN 1558-2361, Vol. 31, p. 2955-2959Article in journal (Refereed) Published
Abstract [en]

This letter considers the design and properties of linear-phase finite-length impulse response (FIR) filters for equalization of the frequency responses of digital-to-analog converters (DACs). The letter derives estimates for the filter orders required, as functions of the bandwidth and equalization accuracy, for four DAC pulses that are used in DACs in multiple Nyquist bands. The estimates are derived through a large set of minimax-optimal equalizers and the use of symbolic regression followed by minimax-optimal curve fitting for further enhancement. Design examples demonstrate the accuracy of the proposed estimates. In addition, the letter discusses the appropriateness of the four types of linear-phase FIR filters, for the different equalizer cases, as well as the corresponding properties of the equalized systems.

Place, publisher, year, edition, pages
IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC, 2024
Keywords
Finite impulse response filters; Equalizers; Accuracy; Delays; Bandwidth; Frequency response; Optimization; Estimation; MATLAB; Frequency conversion; DACs; equalizers; linear-phase FIR filters; symbolic regression; curve fitting; minimax optimization
National Category
Signal Processing
Identifiers
urn:nbn:se:liu:diva-209359 (URN)10.1109/LSP.2024.3483008 (DOI)001342549800004 ()
Note

Funding Agencies|ELLIIT

Available from: 2024-11-12 Created: 2024-11-12 Last updated: 2026-03-19
5. Joint Sampling Frequency Offset Estimation and Compensation Based on the Farrow Structure
Open this publication in new window or tab >>Joint Sampling Frequency Offset Estimation and Compensation Based on the Farrow Structure
2025 (English)In: 2025 25TH INTERNATIONAL CONFERENCE ON DIGITAL SIGNAL PROCESSING, DSP, IEEE , 2025Conference paper, Published paper (Refereed)
Abstract [en]

This paper introduces a sampling frequency offset (SFO) estimation method based on the Farrow structure, which is typically utilized for the SFO compensation and thereby enables a reduction of the implementation complexity of the SFO estimation. The proposed method is implemented in the time domain and works for arbitrary bandlimited signals, thus with no additional constraints on the waveform structure. Moreover, it can operate on only the real or imaginary part of a complex signal, which further reduces the estimation complexity. Furthermore, the proposed method can simultaneously estimate the SFO and additional sampling time offset (STO) and it is insensitive to other synchronization errors, like carrier frequency offset. Both the derivations of the proposed method and its implementation are presented, and through simulation examples, it is demonstrated that it can accurately estimate both SFO and STO for different types of bandlimited signals.

Place, publisher, year, edition, pages
IEEE, 2025
Series
International Conference on Digital Signal Processing, ISSN 1546-1874, E-ISSN 2165-3577
National Category
Signal Processing
Identifiers
urn:nbn:se:liu:diva-219094 (URN)10.1109/DSP65409.2025.11074995 (DOI)001556221900046 ()2-s2.0-105012180434 (Scopus ID)9798331512149 (ISBN)9798331512132 (ISBN)
Conference
9th International Conference on Digital Signal Processing-ICDSP, Chengdu, PEOPLES R CHINA, feb 21-23, 2025
Note

Funding Agencies|ELLIIT and Sweden's Innovation Agency

Available from: 2025-10-29 Created: 2025-10-29 Last updated: 2026-04-02
6. Efficient Computation of Time-Index Powered Weighted Sums Using Cascaded Accumulators
Open this publication in new window or tab >>Efficient Computation of Time-Index Powered Weighted Sums Using Cascaded Accumulators
2026 (English)In: IEEE Signal Processing Letters, ISSN 1070-9908, E-ISSN 1558-2361, Vol. 33, p. 893-897Article in journal (Refereed) Published
Abstract [en]

This letter presents a novel approach for \mbox{efficiently} computing time-index powered weighted sums of the form $\sum_{n=0}^{N-1} n^{K} v[n]$ using cascaded accumulators. Traditional direct computation requires $K{\times}N$ general multiplications, which become prohibitive for large $N$, while alternative strategies based on lookup tables or signal reversal require storing entire data blocks. By exploiting accumulator properties, the proposed method eliminates the need for such storage and reduces the multiplicative cost to only $K{+}1$ constant multiplications, enabling efficient real-time implementation. The approach is particularly useful when such sums need to be efficiently computed in sample-by-sample processing systems.

Place, publisher, year, edition, pages
Institute of Electrical and Electronics Engineers (IEEE), 2026
Keywords
Polynomials;Real-time systems;Costs;Computational efficiency;Transfer functions;Table lookup;Registers;Convolution;Artificial intelligence;Time-frequency analysis;Accumulators;addition-chain exponentiation;binomial coefficients;Stirling numbers;time-index powered weighted sums
National Category
Communication Systems
Identifiers
urn:nbn:se:liu:diva-221366 (URN)10.1109/lsp.2026.3661843 (DOI)001696573400005 ()2-s2.0-105029958842 (Scopus ID)
Projects
ELLIIT, VINNOVA
Note

Funding: ELLIIT; Sweden's Innovation Agency

Available from: 2026-02-18 Created: 2026-02-18 Last updated: 2026-04-02

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