liu.seSearch for publications in DiVA
1314151617181916 of 75
CiteExportLink to record
Permanent link

Direct link
Cite
Citation style
  • apa
  • ieee
  • modern-language-association-8th-edition
  • vancouver
  • oxford
  • Other style
More styles
Language
  • de-DE
  • en-GB
  • en-US
  • fi-FI
  • nn-NO
  • nn-NB
  • sv-SE
  • Other locale
More languages
Output format
  • html
  • text
  • asciidoc
  • rtf
Efficient Signal Processing Algorithms for Reconfigurable Digital Filtering, Synchronization, and Power Amplifier Linearization
Linköping University, Department of Electrical Engineering, Communication Systems. Linköping University, Faculty of Science & Engineering.ORCID iD: 0009-0001-6464-5452
2026 (English)Doctoral thesis, comprehensive summary (Other academic)
Abstract [en]

Complexity reduction and reconfigurability are challenges in the design of modern communication system front-ends. Each new generation of communication standards brings more stringent requirements on data rates, bandwidth, synchronization, and spectral efficiency, which in turn can lead to increased power consumption and chip area. To meet these requirements and at the same time prevent a rapid growth in power consumption and silicon area, it is necessary to develop more sophisticated digital signal processing (DSP) algorithms that simultaneously can achieve high performance, flexibility, and low implementation cost, particularly in hardware-constrained receiver and transmitter front-ends. This thesis investigates efficient signal processing techniques for reconfigurable communication system front-ends and presents contributions in three directions: design and implementation of variable digital filters (VDFs), efficient synchronization techniques, particularly sampling frequency offset (SFO) estimation and compensation using VDFs, and analysis and optimization of cascaded power amplifiers (PAs), specifically their accumulated nonlinearities.

Since digital filters form the core of DSP algorithms, a key candidate for efficient reconfigurability in digital front-ends is the class of VDFs, which are capable of real-time frequency response tuning without the need for online filter design. The main advantage of VDFs is that they require only an adjustment of one or a few parameters to change their characteristics, while the majority of filter coefficients remain fixed after the initial design. This property eliminates the need for extensive online computations and makes VDFs particularly attractive for modern adaptive communication technologies, enabling efficient hardware implementation. In this area, various aspects of design and implementation of VDFs are presented in the thesis, including: (i) implementations and systematic design procedures based on minimax optimization for reconfigurable finite-impulse-response (FIR) filters for simultaneous equalization and lowpass filtering; (ii) an analysis of chip area and power consumption for application-specific integrated circuit (ASIC) implementation of the reconfigurable lowpass equalizer with simultaneously variable bandwidth; (iii) low-complexity frequency-domain implementations of VDFs based on the assumption that these filters have been designed using a common time-domain design approach based on optimizing the impulse response coefficients; (iv) efficient frequency-sampling-based design approaches (minimax based and closed-form least-squares) for a variablebandwidth FIR filter implemented in the frequency domain, allowing for direct optimization of the DFT coefficients considering the filter frequency-domain implementation and thereby resulting in a substantial reduction in implementation complexity.

Further, accurate synchronization is essential for reliable operation of communication systems, as synchronization errors can significantly degrade overall system performance. Among these impairments, SFO is critical, especially in modern wideband and high-speed communication systems, where even tiny differences between sampling clocks lead to a noticeable cumulative timing drift, resulting in inter-carrier and inter-symbol interference. While the SFO compensation is commonly carried out in the time domain, most existing SFO estimation methods are formulated in the frequency domain, which are generally quite computationally demanding, and it results in a separation between estimation and compensation stages. In contrast to these traditional approaches, this thesis presents two contributions in this area, specifically: (i) a joint SFO estimation and compensation framework based on a variable-fractional- delay filter, that results in reduced implementation complexity of the SFO estimation and is applicable to arbitrary bandlimited signals; (ii) a generalized accumulator-based approach for efficient computation of time-index powered weighted sums, which is employed in the proposed SFO estimation algorithms to implement computation of time-index and time-index-squared weighted sums in an efficient way leading to eliminating considerable parts of multiplications.

Finally, recent advances in wireless communication systems have shown the need for a reconfigurable number of cascaded power amplifiers (PAs). While PAs generally constitute one of the main sources of nonlinearities in a transceiver that distort the transmitted signal and degrade the overall system performance, in cascaded PAs, the distortions from each amplifier accumulate with those from the preceding stages, leading to severe nonlinear behavior. Considering the requirements on high efficiency and a maximally linear operation regime, this thesis investigates the effect of total nonlinearities occurring in cascaded PAs by providing results on modeling, analysis, linearization, and optimization of cascaded amplifiers.

Abstract [sv]

Komplexitetsreduktion och avstämbarhet är utmaningar i konstruktion av moderna kommunikationssystems så kallade front-ends. Varje ny generation av kommunikationsstandard medför strängare krav på datahastigheter, bandbredd, synkronisering och spektral effektivitet, vilket i sin tur kan leda till ökad strömförbrukning och chiparea i en hårdvaruimplementering. För att möta dessa krav och samtidigt förhindra ökning av strömförbrukning och kiselarea är det nödvändigt att utveckla mer sofistikerade algoritmer för digital signalbehandling (DSB) som samtidigt kan uppnå en hög prestanda, flexibilitet och låg implementeringskostnad, särskilt i hårdvarubegränsade mottagar- och sändar-front-ends. Denna avhandling studerar effektiva signalbehandlingstekniker och presenterar tre olika bidrag: konstruktion och implementering av avstämbara digitala filter (VDF), effektiva synkroniseringstekniker, särskilt estimering och kompensation av samplingsfrekvensoffset (SFO) med hjälp av VDF, och analys och optimering av kaskadkopplade effektförstärkare (så kallade PA), särskilt deras ackumulerade olinjäriteter.

Eftersom digitala filter utgör kärnan i DSB-algoritmer är en nyckelkandidat för effektiv avstämbarhet i digitala front-ends klassen av VDF:er som kan finjustera frekvenskarakteristiken i realtid utan behov av onlinefilterdesign. Den största fördelen med VDF:er är att de endast kräver en justering av en eller några få parametrar för att ändra sina egenskaper, medan majoriteten av filterkoefficienterna förblir fixa efter den initiala designen. Denna egenskap eliminerar behovet av omfattande online-beräkningar och gör VDF:er särskilt attraktiva för moderna adaptiva kommunikationstekniker, vilket möjliggör effektiv hårdvaruimplementering. Inom detta område presenterar avhandlingen tre olika tekniker för design och implementering av VDF: (i) implementeringar och systematiska designprocedurer baserade på minimaxoptimering för avstämbara så kallade FIR-filter för samtidig frekvensgångsutjämning och lågpassfiltrering; (ii) implementering av den avstämbara lågpassutjämnaren med samtidigt variabel bandbredd, inklusive analys av chiparea och effektförbrukning i applikationsspecifika integrerade kretsar; (iii) effektiva frekvensdomän-implementeringar av VDF:er som konstruerats via filterdesign i tidsdomänen; (iv) effektiva frekvenssamplingsbaserade designmetoder (minimax och minstakvadrat) för FIR-filter med avstämbar bandbredd implementerat i frekvensdomänen, vilket möjliggör direkt optimering av DFT-koefficienterna med hänsyn till filtrets frekvensdomänimplementering och därigenom resulterar i en signifikant minskning av implementeringskomplexiteten.

Vidare är noggrann synkronisering avgörande för tillförlitlig drift av kommunikationssystem, eftersom synkroniseringsfel kan försämra systemets totala prestanda avsevärt. Bland dessa försämringar är SFO kritisk, särskilt i moderna bredbandiga och höghastighetskommunikationssystem, där även små skillnader mellan samplingsklockor leder till en märkbar kumulativ tidsdrift, vilket resulterar i interferens mellan bärvågor och symboler. Medan SFO-kompensationen vanligtvis utförs i tidsdomänen är de flesta befintliga SFO-estimeringsmetoder formulerade i frekvensdomänen, vilka i allmänhet är ganska beräkningskrävande, och det resulterar i en separation mellan estimering och kompensation. I motsats till dessa traditionella metoder presenterar denna avhandling två bidrag inom detta område: (i) ett gemensamt ramverk för SFO-estimering och kompensation baserat på ett avstämbart fördröjningsfilter, vilket resulterar i minskad implementeringskomplexitet för SFO-estimeringen och är tillämpbart på godtyckliga bandbegränsade signaler; (ii) en generaliserad ackumulatorbaserad metod för effektiv beräkning av viktade summor, som används i de föreslagna SFO-estimeringsalgoritmerna för att implementera beräkning av tidsindex-viktade och tidsindexkvadratviktade summor på ett effektivt sätt, vilket leder till att de flesta av multiplikationerna elimineras.

Slutligen har nya framsteg inom trådlösa kommunikationssystem visat behovet av ett avstämbart antal kaskadkopplade PA-steg. Medan en PA i allmänhet är en av de huvudsakliga källorna till olinjäriteter i en sändarmottagare som förvränger den sända signalen och försämrar systemets totala prestanda, ackumuleras felen i kaskadkopplade PA-steg, vilket leder till större olinjäriteter. Med hänsyn till kraven på hög effektivitet och ett maximalt linjärt driftsområde studerar denna avhandling effekten av totala olinjäriteter som uppstår i kaskadkopplade PA-steg genom modellering, analys, linjärisering och optimering.

Place, publisher, year, edition, pages
Linköping: Linköping University Electronic Press, 2026. , p. 87
Series
Linköping Studies in Science and Technology. Dissertations, ISSN 0345-7524 ; 2517
National Category
Communication Systems
Identifiers
URN: urn:nbn:se:liu:diva-222441DOI: 10.3384/9789181185379ISBN: 9789181185362 (print)ISBN: 9789181185379 (electronic)OAI: oai:DiVA.org:liu-222441DiVA, id: diva2:2050544
Public defence
2026-05-13, Ada Lovelace, B Building, Campus Valla, Linköping, 09:00 (English)
Opponent
Supervisors
Note

2026:04-02: The thesis was first published online. The online published version reflects the printed version. 

2026:04-07: The thesis was updated with a new front cover. Before this date the PDF has been downloaded 33 times.

Available from: 2026-04-02 Created: 2026-04-02 Last updated: 2026-04-07Bibliographically approved
List of papers
1. Low-complexity reconfigurable FIR lowpass equalizers for polynomial channel models
Open this publication in new window or tab >>Low-complexity reconfigurable FIR lowpass equalizers for polynomial channel models
2024 (English)In: Digital signal processing (Print), ISSN 1051-2004, E-ISSN 1095-4333, Vol. 150, article id 104533Article in journal (Refereed) Published
Abstract [en]

This paper introduces realizations of a reconfigurable finite -impulse -response (FIR) filter for simultaneous equalization and lowpass filtering. The main advantage of the proposed solutions is computational complexity reduction compared to existing solutions for a given performance, which leads to reduced hardware complexity. The proposed structures employ properties of both a variable bandwidth (VBW) filter and a variable equalizer (VE) with variable coefficients. The overall transfer function of the proposed reconfigurable lowpass equalizer (RLPE) is a weighted linear combination of fixed subfilters where the weights are directly determined by the bandwidth and one or several parameters of the channel needed to be equalized. The paper provides design procedures based on minimax optimization and introduces a fast design method for the filter with several variable parameters that can substantially decrease the design time. Filter order estimation expressions as well as complexity expressions are presented for all proposed realizations. Design examples include comparison of the RLPE structures and a common approach of using a regular FIR equalization filter requiring online redesign when the bandwidth or channel characteristics are changed. It is shown that the number of general multiplications can be reduced up to 91% using the proposed RLPE.

Place, publisher, year, edition, pages
ACADEMIC PRESS INC ELSEVIER SCIENCE, 2024
Keywords
Variable equalizer; Variable bandwidth lowpass filter; Digital differentiator; Polynomial channel model
National Category
Signal Processing
Identifiers
urn:nbn:se:liu:diva-204911 (URN)10.1016/j.dsp.2024.104533 (DOI)001238269500001 ()
Available from: 2024-06-17 Created: 2024-06-17 Last updated: 2026-04-02
2. Low-Complexity Implementation of Real-Time Reconfigurable Low-Pass Equalizers
Open this publication in new window or tab >>Low-Complexity Implementation of Real-Time Reconfigurable Low-Pass Equalizers
2025 (English)In: IEEE Transactions on Very Large Scale Integration (vlsi) Systems, ISSN 1063-8210, E-ISSN 1557-9999, Vol. 33, no 9, p. 2462-2473Article in journal (Refereed) Published
Abstract [en]

Implementation techniques and results for a recently proposed real-time reconfigurable low-pass equalizer (RLPE) consisting of a variable bandwidth (VBW) filter and a variable equalizer (VE) are presented. Both components utilize fixed finite-length impulse response (FIR) filters combined with a few general multipliers, resulting in lower area and power consumption compared to a general FIR filter, despite requiring more multiplications. This is because the constant multipliers in the fixed FIR filters of the RLPE can be optimized for implementation. An additional advantage is that the proposed RLPE does not require online design. Various implementation alternatives for fixed FIR filters, including ways to increase the frequency, are evaluated to optimize the implementation of the RLPE. Several versions of the proposed RLPE and a general FIR filter for comparison are implemented using a 28-nm fully depleted silicon on insulator (FD-SOI) standard cell library. The results demonstrate that the RLPE baseline design requires less power and area than the general equalizer, and although the frequency of the baseline implementation is lower, the design can reach the same frequency while still having significantly less power and area. Furthermore, an approach is introduced to break the chain in the polynomial section of the VBW filter by using fewer additional registers compared to standard pipelining. Instead, this method reformulates the constant multiplication problem to produce correct results. For the considered case, the power consumption is reduced between 49% and 70% for different frequencies, with an area decrease in the range of 64%-67%, by using the proposed RLPE compared to a general FIR filter.

Place, publisher, year, edition, pages
IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC, 2025
Keywords
Constant multiplications; real-time reconfigura-tion; variable bandwidth (VBW) low-pass filter; variable equalizer (VE); variable equalizer (VE); variable equalizer (VE)
National Category
Other Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
urn:nbn:se:liu:diva-216582 (URN)10.1109/TVLSI.2025.3578450 (DOI)001527309900001 ()2-s2.0-105010327462 (Scopus ID)
Note

Funding Agencies|ELLIIT Strategic Research Environment

Available from: 2025-08-22 Created: 2025-08-22 Last updated: 2026-04-02
3. Frequency-Domain Implementations of Variable Digital FIR Filters Using the Overlap-Save Technique
Open this publication in new window or tab >>Frequency-Domain Implementations of Variable Digital FIR Filters Using the Overlap-Save Technique
2023 (English)In: 2023 24th International Conference on Digital Signal Processing (DSP), Institute of Electrical and Electronics Engineers (IEEE), 2023Conference paper, Published paper (Refereed)
Abstract [en]

The paper introduces frequency-domain implementations of variable digital filters using the overlap-save method. Expressions for implementation and design complexities are derived for real-valued impulse responses. Design examples include implementations of a variable bandwidth (VBW) filter alone as well as a cascade of a VBW filter and a variable fractional delay(VFD) filter. Compared to a time-domain implementation and a filter bank approach, the proposed structures can reduce the implementation complexity significantly and achieve savings up to 95% in the multiplication rate and up to 89% in the addition rate.

Place, publisher, year, edition, pages
Institute of Electrical and Electronics Engineers (IEEE), 2023
Series
International Conference on Digital Signal Processing (DSP), ISSN 1546-1874, E-ISSN 2165-3577
Keywords
Variable digital filter, frequency-domain implementations, implementation complexity, overlap-save
National Category
Signal Processing
Identifiers
urn:nbn:se:liu:diva-201232 (URN)10.1109/DSP58604.2023.10167923 (DOI)2-s2.0-85165482542 (Scopus ID)9798350339598 (ISBN)9798350339604 (ISBN)
Conference
24th International Conference on Digital Signal Processing (DSP), Rhodes, Greece, June 11-13, 2023
Available from: 2024-02-28 Created: 2024-02-28 Last updated: 2026-04-02Bibliographically approved
4. Efficient Design and Implementation of Fast-Convolution-Based Variable-Bandwidth Filters
Open this publication in new window or tab >>Efficient Design and Implementation of Fast-Convolution-Based Variable-Bandwidth Filters
2024 (English)In: Proceeeing of 32nd European Signal Processing Conference EUSIPCO 2024, IEEE , 2024, p. 2557-2561Conference paper, Poster (with or without abstract) (Refereed)
Abstract [en]

This paper introduces an efficient design approach for a fast-convolution-based variable-bandwidth (VBW) filter. The proposed approach is based on a hybrid of frequency sampling and optimization (HFSO), that offers significant computational complexity reduction compared to existing solutions for a given performance. The paper provides a design procedure based on minimax optimization to obtain the minimum complexity of the overall filter. A design example includes a comparison of the proposed design-based VBW filter and time-domain designed VBW filters implemented in the time domain and in the frequency domain. It is shown that not only the implementation complexity can be reduced but also the design complexity by excluding any computations when the bandwidth of the filter is adjusted. Moreover, memory requirements are also decreased compared to the existing frequency-domain implementations. Index Terms—Variable bandwidth filter, fast convolution, frequency-domain design, time-varying systems, overlap-save, multirate filter banks.

Place, publisher, year, edition, pages
IEEE, 2024
Series
European Signal Processing Conference, ISSN 2076-1465
National Category
Signal Processing
Identifiers
urn:nbn:se:liu:diva-207039 (URN)001349787000511 ()9789464593617 (ISBN)
Conference
EUSIPCO 2024, 32nd European Signal Processing Conference, August 26-30 2024, Lyon, France
Available from: 2024-08-28 Created: 2024-08-28 Last updated: 2026-04-02Bibliographically approved
5. Closed-Form Least-Squares Design of Fast-Convolution Based Variable-Bandwidth FIR Filters
Open this publication in new window or tab >>Closed-Form Least-Squares Design of Fast-Convolution Based Variable-Bandwidth FIR Filters
2026 (English)In: IEEE Open Journal of Signal Processing, E-ISSN 2644-1322, Vol. 7, p. 54-63Article in journal (Refereed) Published
Abstract [en]

This paper introduces a closed-form least-squares (LS) design approach for fast-convolution (FC) based variable-bandwidth (VBW) finite-impulse-response (FIR) filters. The proposed LS design utilizes frequency sampling and the VBW filter frequency-domain implementation using the overlap-save (OLS) method, that together offer significant savings in implementation and online bandwidth reconfiguration complexities. Since combining frequency-domain design and OLS implementation leads to a linear periodic time-varying (LPTV) behavior of the VBW filter, a set of the corresponding time-invariant impulse responses is considered in the proposed design. Through numerical examples, it is demonstrated that the proposed approach enables not only closed-form design of FC-based VBW filters with substantial complexity reductions compared to existing solutions for a given performance, but also allows the variable bandwidth range to be extended without any increase in complexity. Moreover, a way of reducing the maximum approximation error energy over the whole set of the time-invariant filters of the LPTV system is shown by introducing appropriate weighting functions in the design.

Place, publisher, year, edition, pages
IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC, 2026
Keywords
Finite impulse response filters; Discrete Fourier transforms; Frequency-domain analysis; Filter banks; Complexity theory; Bandwidth; Time-domain analysis; Optimization; Frequency response; Passband; Variable bandwidth filter; fast convolution; overlap-save; frequency-domain design, frequency sampling; time-varying systems; least-squares
National Category
Control Engineering
Identifiers
urn:nbn:se:liu:diva-221137 (URN)10.1109/OJSP.2025.3650439 (DOI)001673852000001 ()2-s2.0-105026494335 (Scopus ID)
Available from: 2026-02-10 Created: 2026-02-10 Last updated: 2026-04-02
6. Joint Sampling Frequency Offset Estimation and Compensation Based on the Farrow Structure
Open this publication in new window or tab >>Joint Sampling Frequency Offset Estimation and Compensation Based on the Farrow Structure
2025 (English)In: 2025 25TH INTERNATIONAL CONFERENCE ON DIGITAL SIGNAL PROCESSING, DSP, IEEE , 2025Conference paper, Published paper (Refereed)
Abstract [en]

This paper introduces a sampling frequency offset (SFO) estimation method based on the Farrow structure, which is typically utilized for the SFO compensation and thereby enables a reduction of the implementation complexity of the SFO estimation. The proposed method is implemented in the time domain and works for arbitrary bandlimited signals, thus with no additional constraints on the waveform structure. Moreover, it can operate on only the real or imaginary part of a complex signal, which further reduces the estimation complexity. Furthermore, the proposed method can simultaneously estimate the SFO and additional sampling time offset (STO) and it is insensitive to other synchronization errors, like carrier frequency offset. Both the derivations of the proposed method and its implementation are presented, and through simulation examples, it is demonstrated that it can accurately estimate both SFO and STO for different types of bandlimited signals.

Place, publisher, year, edition, pages
IEEE, 2025
Series
International Conference on Digital Signal Processing, ISSN 1546-1874, E-ISSN 2165-3577
National Category
Signal Processing
Identifiers
urn:nbn:se:liu:diva-219094 (URN)10.1109/DSP65409.2025.11074995 (DOI)001556221900046 ()2-s2.0-105012180434 (Scopus ID)9798331512149 (ISBN)9798331512132 (ISBN)
Conference
9th International Conference on Digital Signal Processing-ICDSP, Chengdu, PEOPLES R CHINA, feb 21-23, 2025
Note

Funding Agencies|ELLIIT and Sweden's Innovation Agency

Available from: 2025-10-29 Created: 2025-10-29 Last updated: 2026-04-02
7. Efficient Computation of Time-Index Powered Weighted Sums Using Cascaded Accumulators
Open this publication in new window or tab >>Efficient Computation of Time-Index Powered Weighted Sums Using Cascaded Accumulators
2026 (English)In: IEEE Signal Processing Letters, ISSN 1070-9908, E-ISSN 1558-2361, Vol. 33, p. 893-897Article in journal (Refereed) Published
Abstract [en]

This letter presents a novel approach for \mbox{efficiently} computing time-index powered weighted sums of the form $\sum_{n=0}^{N-1} n^{K} v[n]$ using cascaded accumulators. Traditional direct computation requires $K{\times}N$ general multiplications, which become prohibitive for large $N$, while alternative strategies based on lookup tables or signal reversal require storing entire data blocks. By exploiting accumulator properties, the proposed method eliminates the need for such storage and reduces the multiplicative cost to only $K{+}1$ constant multiplications, enabling efficient real-time implementation. The approach is particularly useful when such sums need to be efficiently computed in sample-by-sample processing systems.

Place, publisher, year, edition, pages
Institute of Electrical and Electronics Engineers (IEEE), 2026
Keywords
Polynomials;Real-time systems;Costs;Computational efficiency;Transfer functions;Table lookup;Registers;Convolution;Artificial intelligence;Time-frequency analysis;Accumulators;addition-chain exponentiation;binomial coefficients;Stirling numbers;time-index powered weighted sums
National Category
Communication Systems
Identifiers
urn:nbn:se:liu:diva-221366 (URN)10.1109/lsp.2026.3661843 (DOI)001696573400005 ()2-s2.0-105029958842 (Scopus ID)
Projects
ELLIIT, VINNOVA
Note

Funding: ELLIIT; Sweden's Innovation Agency

Available from: 2026-02-18 Created: 2026-02-18 Last updated: 2026-04-02
8. Modeling, Analysis, and Optimization of Cascaded Power Amplifiers
Open this publication in new window or tab >>Modeling, Analysis, and Optimization of Cascaded Power Amplifiers
2025 (English)In: 2025 33rd European Signal Processing Conference (EUSIPCO), European Association for Signal Processing (EURASIP) , 2025, p. 2692-2696Conference paper, Published paper (Refereed)
Abstract [en]

This paper deals with modeling, analysis, and optimization of power amplifiers (PAs) placed in a cascaded structure, particularly the effect of cascaded nonlinearities is studied by showing potential ways to minimize the total nonlinearities. The nonlinear least-squares algorithm is proposed to optimize the PA parameters along with the input power level, and thereby minimize the total nonlinearities in the cascaded structure. The simulation results demonstrate that the performance of the optimized configurations for up to five PAs using the proposed framework can improve the linearity properties of the overall cascade.

Place, publisher, year, edition, pages
European Association for Signal Processing (EURASIP), 2025
Keywords
Power amplifier nonlinearity, Cascaded structure, Minimization of total nonlinearities, Nonlinear least-squares
National Category
Signal Processing
Identifiers
urn:nbn:se:liu:diva-222440 (URN)10.23919/EUSIPCO63237.2025.11226028 (DOI)9789464593624 (ISBN)9798350391831 (ISBN)
Conference
2025 33rd European Signal Processing Conference (EUSIPCO)
Available from: 2026-04-02 Created: 2026-04-02 Last updated: 2026-04-02Bibliographically approved

Open Access in DiVA

fulltext(3714 kB)17 downloads
File information
File name FULLTEXT02.pdfFile size 3714 kBChecksum SHA-512
9b922cb090b40bef727805983cf5819fa60c970f78d0842a7f1b91a8f5477cd8652ca2e8a7e1ee3f7de77ce24c45232e2d67d391c7030089e6f6879b54f50e39
Type fulltextMimetype application/pdf
Order online >>

Other links

Publisher's full text

Authority records

Moryakova, Oksana

Search in DiVA

By author/editor
Moryakova, Oksana
By organisation
Communication SystemsFaculty of Science & Engineering
Communication Systems

Search outside of DiVA

GoogleGoogle Scholar
Total: 58 downloads
The number of downloads is the sum of all downloads of full texts. It may include eg previous versions that are now no longer available

doi
isbn
urn-nbn

Altmetric score

doi
isbn
urn-nbn
Total: 395 hits
1314151617181916 of 75
CiteExportLink to record
Permanent link

Direct link
Cite
Citation style
  • apa
  • ieee
  • modern-language-association-8th-edition
  • vancouver
  • oxford
  • Other style
More styles
Language
  • de-DE
  • en-GB
  • en-US
  • fi-FI
  • nn-NO
  • nn-NB
  • sv-SE
  • Other locale
More languages
Output format
  • html
  • text
  • asciidoc
  • rtf