A study of the component tolerances on an ultra-wideband low-noise amplifier designed on a conventional printed circuit board is presented in this paper. The low-noise amplifier design employs dual-section input and output microstrip matching networks for wideband operation with a low noise figure and a flat power gain. Firstly, the effect of passive component and manufacturing process tolerances on the low-noise amplifier performance is theoretically studied by means of sensitivity analyses. Secondly, simulation and measurement results are presented for verification of the analytical results. It is shown that, compared with a lumped matching network design, a microstrip matching network design significantly reduces the ultra-wideband low-noise amplifier sensitivity to component tolerances.

An ultrawideband 6-9 GHz six-port correlator is designed and manufactured.Based on this six-port correlator, behavioral models, and true component circuit designs of a transceiver are developed to study the performance of the proposed direct conversion ultrawideband transceiver topology. A new six-port modulator with controllable impedance terminations implemented with a field effect transistor in the linear operation region is presented

A multi-band and ultra-wideband (UWB) 3.1-4.8 GHz receiver front-end consisting of a fully integrated filter and triplexer network, and a flat gain low-noise amplifier (LNA) is presented in this paper. The front-end utilizes a microstrip network and three combined broadside- and edge-coupled bandpass filters to connect the three sub-bands. The LNA design employs dual-section input and output microstrip matching networks for wideband operation with a flat power gain and a low noise figure. The system is fully integrated in a four-metal-layer printed circuit board. The measured power gain is 10 dB and the noise figure of the front-end is 6 dB at each center frequency of the three sub-bands. The minimum isolation between the sub-bands is -27 dB and the isolation between the non-neighboring alternate sub-bands is -52 dB. The out-of-band interferer attenuation is below -30 dB.

Bias networks with radio frequency (RF) chokes can be implemented using different microstrip elements. They can have different advantages in terms of bandwidth and occupied area. However, sharp discontinuities of the transfer functions have been observed in these types of bias networks. In this paper they are explained by resonances generated within the DC path of the bias network. As the resonance behavior degrades the performance of broadband RF circuits, the robustness of different bias networks against resonance was investigated. Different bias networks were fabricated and measured. Both simulation and experimental results show that broadband microstrip bias networks can be optimized to avoid or reduce the resonance phenomena.

An ultra-wideband (UWB) 3.1-4.8 GHz radio front-end consisting of three frequency multiplexed antennas and a low-noise amplifier (LNA) is presented in this paper. Using one antenna for each sub-band and an LNA designed for maximum-flat power gain provides equal performance within the entire frequency band. Frequency multiplexing is used to combine the antennas for multi-band UWB. The LNA is optimized for wideband operation and minimum noise figure. The LNA design employs dual-section input and output matching networks. The antennas, the frequency multiplexing network, the matching networks and the bias circuit of the LNA are all implemented using microstrip lines.

Using our own-developed frequency multiplexing network, a radio architecture for parallel radio signal processing has been proposed for achieving extremely high data rate above 10 Gbit/s. To meet the high requirement on phase linearity, amplitude balance and low noise figure in a very large bandwidth, our own-developed ultra-wideband six-port correlator has been utilized for the modulator and demodulator in the radio architecture.

A 7.5 GHz direct-carrier modulator for multi-level quadrature amplitude modulation (M-QAM) using a wideband 7-8 GHz six-port correlator and four controllable impedance terminations implemented with field-effect transistors (FET) is presented in this paper. The proposed encoding schemes of the reflection-type modulator is based on equal impedance values at I and Q ports, such that Γ3 = Γ4 and Γ5 = Γ6 for every symbol in the constellation diagram. The field-effect transistors are operated at zero drain-source voltage (cold-FET). The FET-impedance termination topology includes a source resistor (RS) and a gate resistor (RG) for symmetrical spreading of the reflection coefficients around the origin. In order to validate the 7.5 GHz six-port modulator with cold-FET impedance terminations, the six-port modulator prototype has been realized on a ROGERS4350B substrate of 0.254-mm thickness and tested with a six-port demodulator (receiver). The six-port modulator was measure to have symbol rates of 10 Msymbol/s with QPSK (= 20 Mbit/s) and 250 Msymbol/s with 16-QAM (= 1 Gbit/s).