This thesis describes some high-performance digital CMOS circuits and the design of these circuits.

The goal is to have a higher utilization of standard CMOS processes in order to increase performance of digital circuits. This is done without the use of aggressive processes. The designs are targeted towards very high clock rate and low power consumption.

At the high level, the design are adjusted to fit into a low level architecture optimized for high performance. The architecture is also optimized for the high level design. The logic style and the flip-flops are selected for high performance.

The digital processing chips presented in this thesis are based on a principle of heavily pipelined uni-directional processing in a data path. The logic is pipelined to a logic depth of one or two gates per pipeline stage. This design method and architecture is used for applications with high throughput processing of data.

Two chips are designed for processing of 10 Gb/s SDH (Synchronous Digital Hierarchy) data, for use in fiber optic transmission systems. They include processing for the framer and deframer functions of a SDH regenerator. The 10 Gb/s is internally processed with 16 bits in parallel at a clock rate of 622 MHz. The chips are implemented in standard 0.6-0.8 μm CMOS.

A quadrature 350 MHz Direct Digital Frequency Synthesizer is implemented in 0.8 μm CMOS. This DDFS is a high-speed compact implementation with on-chip DIA converters for the four-phase output. It calculates the sine and cosine values with a precision of 8 bits and with a frequency resolution below 1 Hz by using a sparse ROM-table and interpolation.

A correlator chip for satellite-based high-performance auto-correlator spectrometers is designed. This chip performs more than 0.5 Tera-Multiply and Accumulate operations per second at a speed of 320 MHz in 1664 multipliers and accumulators. This 58 mm² chip contains 1.6 million transistors and is implemented in a 0.6 μm process. The power consumption per operation is reduced with more than 5 times compared with other implementations, without any reduction in supply voltage. The internal noise level is reduced by dividing the processing and clock signal distribution into blocks with a clock buffer in between.

Finally, two different high-speed multiplexers are presented. A 2.4-Gb/s 4:1 multiplexer and a 4-Gb/s 2:1 multiplexer are implemented in 0.8 μm CMOS. Both multiplexers are designed to be clocked by an external high swing clock.

All chips results have been verified by measurements.