An approach to design and implement fixed-function digital filters using bit-serial arithmetic is proposed. The resulting implementations are maximally fast, i.e., the maximal sample frequency f_max is equal to the upper bound on the sample frequency given by the recursive parts of the algorithm. Such implementations are of interest for use in applications with high throughput or in low-power applications after supply voltage scaling. The throughput of the resulting implementations is comparable to the corresponding bit-parallel implementations while using a fractional amount of hardware resources. The proposed implementation technique can easily be extended to more general recursive algorithms.

A maximally fast implementation is achieved by mapping of the operations in an algorithm to a cyclic schedule involving several sample intervals followed by an isomorphic mapping of the operations to a hardware structure. The ability to find maximally fast implementations with the proposed scheduling method is based on a decoupling of the sample period from the scheduling period. Further, numerical equivalence transformations are applied to the signal-flow graph to find a new algorithm with a reduced iteration period.

Different latency models for the arithmetic operations are proposed and their effect on f_max is discussed. One of the models combined with canonic signed-digit coding of the coefficients yields significantly increased throughput for serial/parallel multipliers. It is shown that the circuit style and the interconnection of processing elements also must be taken into account to determine the iteration period bound. In a number of implementations it is demonstrated that higher throughput is obtained for a recursive filter by increasing the latency of the adders.

New algorithms for full-precision serial computation of squares and serial/serial computation of products that yield minimal latency are derived. The logic realizations of the algorithms are regular and can be partitioned into modular bit-slices suitable for hardware implementation.

A CAD tool is proposed that implements the operation scheduling and performs the hardware mapping. The tool accepts coefficients describing the filter and produces a synthesizable VHDL hardware netlist. The tool is capable of handling three different latency models and two lattice wave digital filter structures.