As the processing capacity of the microelectronic circuits increases, the demands on the interconnects will also increase. Hence, there is a need for higher bandwidth to the chips. This dissertation discusses the possibilities to improve the input data rate to CMOS integrated circuits, which is the most common integrated circuit technology today.

By using several parallel sampling switches, which are operated in an interleaved way, several Gbit/s can be received by one low-swing differential input of a standard-CMOS chip. This concept has been studied together with related issues such as sampling switches, phaselocked loops, phase-frequency detectors, and packaging.

Theoretical expressions for the aperture time of an NMOS sampling switch have been derived and the sampling mechanism is explained with regards to time resolution. The theoretical expressions predict a minimum aperture time of 21 ps for an optimal switch in a 0.8-μm process. This switch is able to sample single bits of a 48-Gbit/s data stream. Further, transient 2-D device simulations of an NMOS switch with a 50-Gbit/s data stream as input shows correct sampling.

Experiments show correct sampling of a 16-Gbit/s data stream with a 0.8-μm CMOS circuit. The bit rate was limited by the measurement setup. Circuit simulations of the sampling circuit, including the package, show sampling of 25-Gbit/s data streams.

The generation of the control signals to the sampling switches must be very accurate. The needed skew between two adjacent control signals is of the order of a bit length or less. This accuracy is not provided directly by the CMOS technology.

Experiments with digital delay lines as generators for the control signals show correct operation of a test receiver circuit with external tuning at 2 Gbit/s. Later measurements with better equipment on the same circuit show 5-Gbit/s reception when the circuit is used as a half demultiplexer.

A control system, a phase-lock loop (PLL), is needed to automatically compensate for the process and operation variations in the control-signal generator. One part of a PLL is the phasefrequency detector (PFD). A novel PFD called ncPFD has been developed. It is simple, fast, that is, 800 MHz according to circuit simulations on an extracted-layout netlist of a standard-sized circuit in a 0.8-μm process, and has no dead zone in the phase characteristics. The dead zone is a source of phase jitter. A 200-MHz third-order charge-pump PLL using the ncPFD was tested successfully.

The behavior of this PLL has been analyzed with theoretical and behavioral-simulation methods. Comparisons have been made between them, and to measurements. The comparisons show that the behavioral simulations and the theory matches well. The predicted natural frequency agree well with the measured. However, the damping factor does not agree for the predicted and the measured. One reason for this is that the delay in the control loop is not included in the theory. Behavioral simulations show that increased delay decreases the damping factor. Further, simple expressions for the natural frequency and the damping factor have been developed for the case where the damping factor is small. This since the exact expressions are very tedious to obtain and cumbersome to use.

The multi-Gbit/s bit rates make it impossible to use standard packages since they do not allow these speeds. Specially designed Chip-on-board, COB, packages have been investigated and used for the Gbit/s experiments. The packages and the pad frames was co-designed to match each other to make it possible to use short (~1 mm) bond wires. An FR4-laminate COB package with 50-Ω microstrip wires was used in measurements up to 6 Gbit/s. A microwave-type A1₂0₃-substrate package with 50-Ω microstrip wires has been used up to 16-Gbit/s measurements.