Application Specific Integrated Circuits (ASICs) have been playing a vital role in the semiconductor industry due to advantages like compact design, better power consumption, and better performance, among other things in comparison to general application integrated circuits (ICs). Unlike software applications, which can be tested post-deployment, thorough testing and verification are of utmost importance during the design of an ASIC, which is one of the reasons why a major portion of time is spent on ASIC verification. Having an optimized and reusable verification flow significantly reduces the time-to-market in a competitive industry like IC manufacturing. UVM-based verification is widely adopted for Intellectual Property (IP) verification due to its ability to reuse verification environments for multiple IPs. This thesis focuses on optimizing an existing verification flow for an ASIC IP by using a decimation filter as a case study. The filter is used as a reference model to test the Device Under Test (DUT) model by integrating it into a UVM testbench. The flow developed in the thesis is aimed at providing an efficient, reusable, and good time-to-market verification environment for ASICs.