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Analysis of Graph Processing in Reconfigurable Devices for Edge Computing Applications
Dept. Electrical & Electronics Engineering, University of Bristol, Bristol, UK.
Dept. Electrical & Electronics Engineering, University of Bristol, Bristol, UK.
Linköping University, Department of Electrical Engineering, Computer Engineering. Linköping University, Faculty of Science & Engineering.ORCID iD: 0000-0002-5153-5481
2022 (English)In: 2022 25th Euromicro Conference on Digital System Design (DSD), Institute of Electrical and Electronics Engineers (IEEE), 2022, p. 16-23Conference paper, Published paper (Refereed)
Abstract [en]

Graph processing is an area that has received significant attention in recent years due to the substantial expansion in industries relying on data analytics. Alongside the vital role of finding relations in social networks, graph processing is also widely used in transportation to find optimal routes and biological networks to analyse sequences. The main bottleneck in graph processing is irregular memory accesses rather than computation intensity. Since computational intensity is not a driving factor, we propose a method to perform graph processing at the edge more efficiently. We believe current cloud computing solutions are still very costly and have latency issues. The results demonstrate the benefits of a dedicated sparse graph processing algorithm compared with dense graph processing when analysing data with low density. As graph datasets grow exponentially, traversal algorithms such as breadth-first search (BFS), fundamental to many graph processing applications and metrics, become more costly to compute. Our work focuses on reviewing other implementations of breadth-first search algorithms designed for low power systems and proposing our solution that utilises advanced enhancements to achieve a significant performance boost up to 9.2x better performance in terms of MTEPS compared to other state-of-the-art solutions with a power usage of 2.32W.

Place, publisher, year, edition, pages
Institute of Electrical and Electronics Engineers (IEEE), 2022. p. 16-23
Series
EUROMICRO Conference Proceedings, ISSN 1089-6503
Keywords [en]
graph processing, graph, FPGA, low-cost, breadth-first, search, bfs, zedboard, edge, computing
National Category
Computer Sciences
Identifiers
URN: urn:nbn:se:liu:diva-190906DOI: 10.1109/DSD57027.2022.00012ISI: 000946536500010ISBN: 9781665474047 (electronic)ISBN: 9781665474054 (print)OAI: oai:DiVA.org:liu-190906DiVA, id: diva2:1724472
Conference
25th Euromicro Conference on Digital System Design (DSD), Maspalomas, Spain, 31 August - 02 September 2022
Funder
Wallenberg AI, Autonomous Systems and Software Program (WASP)Available from: 2023-01-07 Created: 2023-01-07 Last updated: 2023-04-13Bibliographically approved

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Nunez-Yanez, Jose Luis

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Total: 95 hits
CiteExportLink to record
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Cite
Citation style
  • apa
  • ieee
  • modern-language-association-8th-edition
  • vancouver
  • oxford
  • Other style
More styles
Language
  • de-DE
  • en-GB
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  • nn-NO
  • nn-NB
  • sv-SE
  • Other locale
More languages
Output format
  • html
  • text
  • asciidoc
  • rtf