Graph Neural Networks (GNNs) are renowned for their ability to process data with irregular structures, making them invaluable in various fields. However, their high computational requirements pose a challenge for efficient inference. In this context, Graph Convolutional Networks (GCNs), a prominent type of GNN, derive their effectiveness from their architecture, which involves layers of graph convolutions and subsequent activation functions. These elements are pivotal in determining the overall runtime of GCNs. Addressing the need for enhanced efficiency, this paper introduces an innovative approach that integrates specialized Activation Functions within a graph Accelerator for Multi-layer GCNs. Our strategy mitigates the need for external memory transfers by positioning the activation function accelerator immediately after the GCN accelerator so that the output remains in the local FPGA memory. This method also incorporates sparse matrix compression and multi-threading to reduce unnecessary data storage and computations, thereby optimizing memory bandwidth and computational efficacy on the Zynq Ultrascale device. A noteworthy aspect of our approach is the adaptation of the Softmax Activation Function to be in a hardware-friendly format, utilizing base replacement and low-precision calculations. This hardware/software co-designed multilayer GCN architecture utilizes PyTorch functions executed on a multi-core ARM CPU, in conjunction with the accelerator which is described in a High-level synthesis (HLS) and is implemented on an AMD/Xilinx Zynq Ultrascale+ FPGA. Our results demonstrate significant performance enhancements, with speedups reaching up to 78.5x for Hardmax and 17.4x for Softermax, compared to traditional software implementations. Importantly, the Softermax variant achieves these speedups with minimal impact on accuracy, while other activation functions maintain reference-level accuracy.