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  • 101.
    Attrell, Henrik
    et al.
    Linköping University, Department of Electrical Engineering, Integrated Circuits and Systems.
    Holmqvist, Mattias
    Linköping University, Department of Electrical Engineering, Integrated Circuits and Systems.
    Utveckling av en kompakt BLE-modul i en portabel EKG: Med möjlighet till kontinuerlig dataöverföring2022Independent thesis Basic level (university diploma), 10,5 credits / 16 HE creditsStudent thesis
    Abstract [en]

    Electrocardiography or ECG is used in healthcare to measure the electrical activity of the heart using several electrodes that are placed on the body. From the measurements, indications of heart diseases and heart rhythm disorders can be detected and then treated. Cardiovascular disease is the most common cause of death in Sweden and the need for ECG examinations is great. Usually the ECG devices are large, awkward, and limited to hospitals as they are complicated and expensive. Linköping University's research group together with several bachelor thesis projects has developed a prototype of a compact and portable ECG. The portable ECG device is connected to a bra that is integrated with electrodes and should be used mainly by women, as the range of user-friendly ECGs for women is small.

    The previously portable ECG is made up of two modules, the ECG module, and the Nordic Thingy52. The ECG module is designed on a specially adapted circuit board that performs the actual measurement of the electrodes and calculations. It is then paired with Thingy52 which is responsible for the wireless communication to other devices via Bluetooth Low Energy or BLE as it is also called. The BLE module, which included Thingy52 and the modified source code from previous work, managed some wireless communication but was considered too slow and could not handle continuous data transfer.

    From the previous work questions arose as to whether it was possible to further develop the previous BLE module by improving data transfer and introducing more features. The most desired features were to optimize the module's data transfer to become continuous, implement functionality to save measured values as a type of backup and implement a simple digital filter to filter out noise and disturbances of the measured values. In addition to this, a more compact and smaller circuit board for the BLE module would also be developed that would replace the Thingy52.

    The project began with acquiring knowledge and understanding of how existing and additional functions or services work and how they should be implemented. Choices about which components and development environments would be used during the project were determined. The choice resulted in continuing with the previous System-on-chip, SoC nRF52832 from Nordic Semiconductor around which Thingy52 is designed. As a result, existing development boards could be used and the circuit diagram from Thingy52 could be reused for the new circuit diagram. Before the self-created circuit board could be ordered and tested, verification was needed to determine that the selected SoC was capable of continuous data transfer. This could be done on development card nRF52 SDK with the same type of SoC. The verification of the data transfer was more time consuming than had been expected and unfortunately there was no time to order the circuit board and therefore could not be tested in practice. A circuit diagram was nevertheless performed which has smaller dimensions than Thingy52 and contains the desired parts.

    During the development of the BLE function, it was chosen to use Nordic's new development environment as it simplified programming of advanced functions, like BLE. The choice to change the development environment, however, resulted in the previous programming code, which handled configuration and data transfer with the ECG module, having to be converted to a new operating system after Nordic switched to the Zypher operating system. As a result, functions and libraries were not supported or did not exist. After this, the focus shifted to implementing and integrating the storage function with the BLE and ECG functions. The multithreading tool was introduced to perform and optimize the functions of the BLE module. Lack of time meant that only placeholders for future implementation of digital filters could be performed. Based on the test results over the BLE module, it is also difficult to guarantee that the SoC has time to perform filtering of measurement data during the already limited time interval.

    After some problems and many tests, the bachelor thesis project finally resulted in a compact circuit that could replace Thingy52. Also, a BLE module that can perform data transfer with some continuity and at the same time store measurement data to a SD card without affecting the communication with the ECG module or the user interface. The end product also has many opportunities to be expanded in future work.

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  • 102.
    Azizi, Kaveh
    Linköping University, Department of Electrical Engineering, Electronics System.
    FPGA Implementation of a Multimode Transmultiplexer2010Independent thesis Advanced level (degree of Master (Two Years)), 30 credits / 45 HE creditsStudent thesis
    Abstract [en]

    As the complexity of Very Large Scale Integration (VLSI) circuits dramatically increases by improvements of technology, there is a huge interests to shift different applications from analog to digital domain. While there are many platform available for this shift, Field Programmable Gate Arrays (FPGAs) hold an attractive position because of their performance, power consumption and configurability. Comparing with Application Specific Integrated Circuit (ASIC) and Digital Signal Processor (DSP), FPGA stands in the middle. It is easier to implement a function on FPGA than ASIC which is to perform a fixed operation. Although, DSP can implement versatile functions, its computational power is not high enough to support the high data rate of FPGA.

    This report is the outcome and result of a master thesis at University of Linköping, Sweden. This report tries to cover both theoretical and hardware aspects of implementation of a Farrow structure for sample rate conversion on FPGA.

    The intention of this work was to contribute to what is nowadays the main focus of communication engineers: designing flexible radio systems. Flexible radio systems are interactive and dynamic by definition. That is why a low-cost, flexible multimode terminal is crucially important to support different telecommunication standards and scenarios. In this thesis, FPGA implementation of complete Farrow system is presented. Matlab/Simulink, and VHDL are used in this thesis work as the prime software.

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  • 103.
    Azmat, Rehan
    Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
    Design and implementation of a low-noise high-linearity variable gain amplifier for high speed transceivers2012Independent thesis Advanced level (degree of Master (Two Years)), 20 credits / 30 HE creditsStudent thesis
    Abstract [en]

    The variable gain amplifier (VGA) is utilized in various applications of remote sensing and communication equipments. Applications of the variable gain amplifier (VGA) include radar, ultrasound, wireless communication and even speech analysis. These applications use the variable gain amplifier (VGA) to enhance dynamic performance.

    The purpose of the thesis work is to implement a high linearity and low noise variable gain amplifier in 150 nm CMOS technology, for an analog-front-end of a transceiver. Two different amplifier architectures are designed and compared. First architecture is an amplifier with diode connected load and second architecture is a source degenerative amplifier. The performance of the amplifier with diode connected load is lower than the source degenerative amplifier in terms of gain, power, linearity, noise and bandwidth. So, the source degenerative amplifier is selected for implementation. The three stage variable gain differential amplifier is implemented with selected architecture.

    The implemented three stage variable gain differential amplifier have gain range of -541.5 mdB to 22.46 dB with step size of approximately 0.3 dB and total gain steps are 78. The -3 dB bandwidth achieved is 953.3 MHz. The third harmonic distortion (HD3) is -45 dBc at 250 mV and the power is 35 mW at 1.8 V supply source.

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  • 104.
    Baaklini, Fredrik
    et al.
    Linköping University, Department of Science and Technology, Physics and Electronics. Linköping University, Faculty of Science & Engineering.
    Bohman, Nicklas
    Linköping University, Department of Science and Technology, Physics and Electronics. Linköping University, Faculty of Science & Engineering.
    Design of a high-precision energy meter according to the Measuring Instruments Directive2018Independent thesis Advanced level (degree of Master (Two Years)), 20 credits / 30 HE creditsStudent thesis
    Abstract [en]

    This thesis investigates how an energy meter should be constructed in order to apply to the Measurement Instrument Directive. The measuring instrument directive is a statutory industry standard. All meters used for billing purposes must abide by this standard. Multiple systems were investigated in order to find the optimal system according to the agreed upon demands. Each system is presented individually and need to be able to withstand 230V and 35A. The system which fulfills the demands the best is implemented. The choosen system is based around the M90E32AS and Atmega328pb IC:s from Microchip. The sensors used are current transformers and voltage dividers. The M90E32AS samples data from the sensors and forwards it to the Atmega328pb where they can be read by a computer. Communication is conducted via SPI (Serial Peripheral Interface). Isolation is needed to provide protection to low voltage components and other equipment. Because of this the transformers and optocouplers are used. The end result is a functioning energy meter. It measures voltage and current in a satisfying way with a very small margin om error. According to the test made regarding energymetering the measurement error is just above 1%. This is a bigger error than what was wanted but the tests are not very precise and the error is probably smaller in reality.

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    Design of a high-precision energy meter according to the Measuring Instruments Directive
  • 105.
    Babar, Haji Akbar
    et al.
    Linköping University, Department of Science and Technology, Physics and Electronics. Linköping University, The Institute of Technology.
    Khattak, Atif
    Linköping University, Department of Science and Technology, Physics and Electronics. Linköping University, The Institute of Technology.
    Design of Dual Band Patch Antenna Array2012Independent thesis Advanced level (degree of Master (Two Years)), 20 credits / 30 HE creditsStudent thesis
    Abstract [en]

    Low profile antennas are very useful in applications such as missile, aircraft, cellular applications and satellites, because in these types of applications, some commonly important constraints are cost, size, weight, performance and easy installation. Microstrip patch antenna fits quite comfortably in this category.

    This thesis work aimed to design the dual band microstrip patch antenna arrays operating at frequencies of 3.5 GHz and 5.0 GHz. Two schemes were used to design the antenna array which is the antenna array with same patch size and antenna array with alternating patch size. Different array configuration with 2, 4, 8 and 16 elements were designed and simulated in Agilent Inc EDA tool ADS using Roger RO4350B substrate with a height of 1.524 mm, and transmission-line model was used for the analysis. Array configuration with 2, 4 and 8 elements were fabricated, and results were measured with the help of the network analyzer in the Lab. Distinct antenna parameters were studied such as VSWR, impedance bandwidth, gain, directivity, antenna radiation efficiency, axial ratio and radiation pattern to evaluate the performance of antennas. Focusing on impedance bandwidth it can be claimed that the microstrip patch antenna arrays have better performance as compared to the single microstrip patch antenna designed.

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  • 106.
    Backenius, Erik
    Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
    On Reduction of Substrate Noise in Mixed-Signal Circuits2005Licentiate thesis, comprehensive summary (Other academic)
    Abstract [en]

    Microelectronics is heading towards larger and larger systems implemented on a single chip. In wireless communication equipment, e.g., cellular phones, handheld computers etc., both analog and digital circuits are required. If several integrated circuits (ICs) are used in a system, a large amount of the power is consumed by the communication between the ICs. Furthermore, the communication between ICs is slow compared with on-chip communication. Therefore, it is favorable to integrate the whole system on a single chip, which is the objective in the system-on-chip (SoC) approach.

    In a mixed-signal SoC, analog and digital circuits share the same chip. When digital circuits are switching, they produce noise that is spread through the silicon substrate to other circuits. This noise is known as substrate noise. The performance of sensitive analog circuits is degraded by the substrate noise in terms of, e.g., lower signal-to-noise ratio and lower spurious-free dynamic range. Another problem is the design of the clock distribution net, which is challenging in terms of obtaining low power consumption, sharp clock edges, and low simultaneous switching noise.

    In this thesis, a noise reduction strategy that focus on reducing the amount of noise produced in digital clock buffers, is presented. The strategy is to use a clock with long rise and fall times. It is also used to relax the constraints on the clock distribution net, which also reduce the design effort. Measurements on a test chip show that the strategy can be implemented in an IC with low cost in terms of speed and power consumption. Comparisons between substrate coupling in silicon-on-insulator (SOI) and conventional bulk technology are made using simple models. The objective here is to get an understanding of how the substrate coupling differs in SOI from the bulk technology. The results show that the SOI has less substrate coupling when no guard band is used, up to a certain frequency that is highly dependent of the chip structure. When a guard band is introduced in one of the analyzed test structures, the bulk resulted in much higher attenuation compared with SOI. An on-chip measurement circuit aiming at measuring simultaneous switching noise has also been designed in a 0.13 µ SOI process.

    List of papers
    1. A strategy for reducing clock noise in mixed-signal circuits
    Open this publication in new window or tab >>A strategy for reducing clock noise in mixed-signal circuits
    2002 (English)In: Proc. IEEE 45th Midwest Symp. on Circuits and Systems, MWSCAS'02, 2002, Vol. 1, p. 29-32Conference paper, Published paper (Refereed)
    Abstract [en]

    Digital switching noise is of major concern in mixed-signal circuits due to the coupling of the noise via a shared substrate to the analog circuits. A significant noise source in this context is the digital clock network that generally has a high switching activity. There is a large capacitive coupling between the clock network and the substrate. Switching of the clock produces current peaks causing simultaneous switching noise (SSN). Sharp clock edges yields a high frequency content of the clock signal and a large SSN. High frequency noise is less attenuated through the substrate than low frequencies due to the parasitic inductance of the interconnect from on-chip to off-chip. In this work, we present a strategy that targets the problems with clock noise. The approach is to generate a clock with smooth edges, i.e. reducing both the high frequency components of the clock signal and the current peaks produced in the power supply. We use a special digital D flip-flop circuit that operates well with the clock. A test chip has been designed where we can control the rise and fall time of the clock edges in a digital FIR filter, and measure the performance of a fifth-order analog active-RC filter.

    Keywords
    FIR filters, RC circuits, active filters, clocks, flip-flops, integrated circuit noise, mixed analog-digital integrated circuits
    National Category
    Other Electrical Engineering, Electronic Engineering, Information Engineering
    Identifiers
    urn:nbn:se:liu:diva-14442 (URN)0-7803-7523-8 (ISBN)
    Available from: 2007-05-22 Created: 2007-05-22 Last updated: 2023-09-05
    2. Design of circuits for a robust clocking scheme
    Open this publication in new window or tab >>Design of circuits for a robust clocking scheme
    2004 (English)In: Proc. 12th Mediterranean Electrotechnical Conf., MELECON'04, 2004, Vol. 1, p. 185-188Conference paper, Published paper (Refereed)
    Abstract [en]

    The design of a clock distribution network in a digital integrated circuit is challenging in terms of obtaining low power consumption, low waveform degradation, low clock skew and low simultaneous switching noise. In this work we aim at alleviating these design restrictions by using a clock buffer with reduced size and a D flip-flop circuit with relaxed constraints on the rise and fall times of the clock. According to simulations the energy dissipation of a D flip-flop, implemented in a 0.35 μm process, increases with only 21% when the fall time of the clock is increased from 0.05 ns to 7.0 ns. Considering that smaller clock buffers can be used there is a potential of power savings by using the suggested clocking scheme.

    Keywords
    buffer circuits, circuit noise, circuit simulation, clocks, digital integrated circuits, flip-flops, integrated circuit modelling, low-power electronics
    National Category
    Other Electrical Engineering, Electronic Engineering, Information Engineering
    Identifiers
    urn:nbn:se:liu:diva-14443 (URN)10.1109/MELCON.2004.1346804 (DOI)0-7803-8271-4 (ISBN)
    Available from: 2007-05-22 Created: 2007-05-22 Last updated: 2023-09-05
    3. Evaluation of a clocking strategy with relaxed constraints on clock edges
    Open this publication in new window or tab >>Evaluation of a clocking strategy with relaxed constraints on clock edges
    2004 (English)In: Proc. TENCON'04, 2004, Vol. 4, p. 411-414Conference paper, Published paper (Refereed)
    Abstract [en]

    A strategy that aims at relaxing the design of the clock network in digital circuits is evaluated through simulations and measurements on a test circuit. In the strategy a clock with long rise and fall times is used in conjunction with a D flip-flop that operates well with this clock. The test circuit consists of a digital FIR filter and a clock buffer with adjustable driving strength. It was designed and manufactured in a 0.35 μm CMOS process. The energy dissipation of the circuit increased 14% when the rise and fall times of the clock increased from 0.5 ns to 10 ns. The corresponding increase in propagation delay was less than 0.5 ns, i.e. an increase of 50% in propagation delay of the register. The results in this paper show that the clocking strategy can be implemented with low costs of power and speed.

    Keywords
    CMOS logic circuits, FIR filters, clocks, delays, flip-flops
    National Category
    Other Electrical Engineering, Electronic Engineering, Information Engineering
    Identifiers
    urn:nbn:se:liu:diva-14444 (URN)10.1109/TENCON.2004.1414957 (DOI)0-7803-8560-8 (ISBN)
    Available from: 2007-05-22 Created: 2007-05-22 Last updated: 2023-09-05
    4. Introduction to substrate noise in SOI CMOS integrated circuits
    Open this publication in new window or tab >>Introduction to substrate noise in SOI CMOS integrated circuits
    2005 (English)In: Proc. National Conf. on Radio Science, RVK'05, 2005Conference paper, Published paper (Other academic)
    Abstract [en]

    In this paper an introduction to substrate noise in silicon oninsulator (SOI) is given. Differences between substratenoise coupling in conventional bulk CMOS and SOICMOS are discussed and analyzed by simulations. The efficiencyof common substrate noise reduction methods arealso analyzed. Simulation results show that the advantageof the substrate isolation in SOI is only valid up to a frequencythat highly depends on the chip structure. In bulk,guard bands are normally directly connected to the substrate.In SOI, the guard bands are coupled to the substratevia the parasitic capacitance of the silicon oxide. Therefore,the efficiency of a guard may be much larger in aconventional bulk than in SOI. One opportunity in SOI isthat a much higher resistivity of the substrate can be used,which results in a significantly higher impedance up to afrequency where the coupling is dominated by the capacitivecoupling of the substrate.

    National Category
    Other Electrical Engineering, Electronic Engineering, Information Engineering
    Identifiers
    urn:nbn:se:liu:diva-14447 (URN)
    Available from: 2007-05-22 Created: 2007-05-22 Last updated: 2023-09-05
    5. Programmable reference generator for on-chip measurement
    Open this publication in new window or tab >>Programmable reference generator for on-chip measurement
    2006 (English)In: Proc. 24th IEEE Norchip Conf., NORCHIP'06, 2006, p. 89-92Conference paper, Published paper (Refereed)
    Abstract [en]

    In this work, circuits for on-chip measurement and periodic waveform capture are designed. The aim is to analyze disturbances in mixed-signal chips such as simultaneous switching noise and the transfer of substrate noise. A programmable reference generator that replaces the standard digital-to-analog converter is proposed. It is based on a resistor string that is connected in a circular structure. A feature is that the reference outputs to the different comparators in the measurement channels are distributed over the nodes of the resistor string. Comparing with using a complete digital-to-analog converter, the use of a buffer is avoided. Hence, there is a potential reduction in the parasitic capacitance and power consumption as well as an increase in speed. We present results from a test chip demonstrating that simultaneous switching noise can be measured with the presented approach.

    Keywords
    comparators, digital-analog conversion, electric noise measurement, integrated circuit measurement, integrated circuit noise, programmable circuits, reference circuits
    National Category
    Other Electrical Engineering, Electronic Engineering, Information Engineering
    Identifiers
    urn:nbn:se:liu:diva-14448 (URN)10.1109/NORCHP.2006.329251 (DOI)1-4244-0772-9 (ISBN)
    Available from: 2007-05-22 Created: 2007-05-22 Last updated: 2023-09-05
    Download full text (pdf)
    FULLTEXT01
  • 107. Order onlineBuy this publication >>
    Backenius, Erik
    Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
    Reduction of Substrate Noise in Mixed-Signal Circuits2007Doctoral thesis, comprehensive summary (Other academic)
    Abstract [en]

    In many consumer products, e.g., cellular phones and handheld computers, both digital and analog circuits are required. Nowadays, it is possible to implement a large subsystem or even a complete system, that earlier required several chips, on a single chip. A system on chip (SoC) has generally the advantages of lower power consumption and a smaller fabrication cost compared with multi-chip solutions. The switching of digital circuits generates noise that is injected into the silicon substrate. This noise is known as substrate noise and is spread through the substrate to other circuits. The substrate noise received in an analog circuit degrades the performance of the circuit. This is a major design issue in mixed-signal ICs where analog and digital circuits share the same substrate.

    Two new noise reduction methods are proposed in this thesis work. The first focuses n reducing the switching noise generated in digital clock buffers. The strategy is to use a clock with long rise and fall times in conjunction with a special D flip-flop. It relaxes the constraints on the clock distribution net, which also reduce the design effort. Measurements on a test chip implemented in a 0.35 μm CMOS technology show that the method can be implemented in an IC with low cost in terms of speed and power consumption. A noise reduction up to 50% is obtained by using the method. The measured power consumption of the digital circuit, excluding the clock buffer, increased 14% when the rise and fall times of the clock were increased from 0.5 ns to 10 ns. The corresponding increase in propagation delay was less than 0.5 ns corresponding to an increase of 50% in propagation delay of the registers.

    The second noise reduction method focuses on reducing simultaneous switching noise below half the clock frequency. This frequency band is assumed to be the signal band of an analog circuit. The idea is to use circuits that have as close to periodic power supply currents as possible to obtain low simultaneous switching noise below the clock in the frequency domain. For this purpose we use precharged differential cascode switch logic together with a novel D flip-flop. To evaluate the method two pipelined adders have been implemented on transistor level in a 0.13 μm CMOS technology, where the novel circuit is implemented with our method and the reference circuit with static CMOS logic together with a TSPC D flip-flop. According to simulation results, the frequency components in the analog signal band can be attenuated from 10 dB up to 17 dB using the proposed method. The cost is mainly an increase in power consumption of almost a factor of three.

    Comparisons between substrate coupling in silicon-on-insulator (SOI) and conventional bulk technology are made using simple models. The objective is to get an understanding of how the substrate coupling differs in SOI from the bulk technology. The results show that the SOI has less substrate coupling if no guard band is used, up to a certain frequency that is dependent of the test case. Introducing a guard band resulted in a higher attenuation of substrate noise in bulk than in SOI.

    An on-chip measurement circuit aiming at measuring simultaneous switching noise has been designed in a 0.13 μm SOI CMOS technology. The measuring circuit uses a single comparator per channel where several passes are used to capture the waveform. Measurements on a fabricated testchip indicate that the measuring circuit works as intended.

    A small part of this thesis work has been done in the area of digit representation in digital circuits. A new approach to convert a number from two’s complement representation to a minimum signed-digit representation is proposed. Previous algorithms are working either from the LSB to the MSB (right-to-left) or from the MSB to the LSB (left-to-right). The novelty in the proposed algorithm is that the conversion is done from left-to-right and right-to-left concurrently. Using the proposed algorithm, the critical path in a conversion circuit can be nearly halved compared with the previous algorithms. The area and power consumption, of the implementation of the proposed algorithm, are somewhere between the left-to-right and right-to-left implementations.

    List of papers
    1. A strategy for reducing clock noise in mixed-signal circuits
    Open this publication in new window or tab >>A strategy for reducing clock noise in mixed-signal circuits
    2002 (English)In: Proc. IEEE 45th Midwest Symp. on Circuits and Systems, MWSCAS'02, 2002, Vol. 1, p. 29-32Conference paper, Published paper (Refereed)
    Abstract [en]

    Digital switching noise is of major concern in mixed-signal circuits due to the coupling of the noise via a shared substrate to the analog circuits. A significant noise source in this context is the digital clock network that generally has a high switching activity. There is a large capacitive coupling between the clock network and the substrate. Switching of the clock produces current peaks causing simultaneous switching noise (SSN). Sharp clock edges yields a high frequency content of the clock signal and a large SSN. High frequency noise is less attenuated through the substrate than low frequencies due to the parasitic inductance of the interconnect from on-chip to off-chip. In this work, we present a strategy that targets the problems with clock noise. The approach is to generate a clock with smooth edges, i.e. reducing both the high frequency components of the clock signal and the current peaks produced in the power supply. We use a special digital D flip-flop circuit that operates well with the clock. A test chip has been designed where we can control the rise and fall time of the clock edges in a digital FIR filter, and measure the performance of a fifth-order analog active-RC filter.

    Keywords
    FIR filters, RC circuits, active filters, clocks, flip-flops, integrated circuit noise, mixed analog-digital integrated circuits
    National Category
    Other Electrical Engineering, Electronic Engineering, Information Engineering
    Identifiers
    urn:nbn:se:liu:diva-14442 (URN)0-7803-7523-8 (ISBN)
    Available from: 2007-05-22 Created: 2007-05-22 Last updated: 2023-09-05
    2. Design of circuits for a robust clocking scheme
    Open this publication in new window or tab >>Design of circuits for a robust clocking scheme
    2004 (English)In: Proc. 12th Mediterranean Electrotechnical Conf., MELECON'04, 2004, Vol. 1, p. 185-188Conference paper, Published paper (Refereed)
    Abstract [en]

    The design of a clock distribution network in a digital integrated circuit is challenging in terms of obtaining low power consumption, low waveform degradation, low clock skew and low simultaneous switching noise. In this work we aim at alleviating these design restrictions by using a clock buffer with reduced size and a D flip-flop circuit with relaxed constraints on the rise and fall times of the clock. According to simulations the energy dissipation of a D flip-flop, implemented in a 0.35 μm process, increases with only 21% when the fall time of the clock is increased from 0.05 ns to 7.0 ns. Considering that smaller clock buffers can be used there is a potential of power savings by using the suggested clocking scheme.

    Keywords
    buffer circuits, circuit noise, circuit simulation, clocks, digital integrated circuits, flip-flops, integrated circuit modelling, low-power electronics
    National Category
    Other Electrical Engineering, Electronic Engineering, Information Engineering
    Identifiers
    urn:nbn:se:liu:diva-14443 (URN)10.1109/MELCON.2004.1346804 (DOI)0-7803-8271-4 (ISBN)
    Available from: 2007-05-22 Created: 2007-05-22 Last updated: 2023-09-05
    3. Evaluation of a clocking strategy with relaxed constraints on clock edges
    Open this publication in new window or tab >>Evaluation of a clocking strategy with relaxed constraints on clock edges
    2004 (English)In: Proc. TENCON'04, 2004, Vol. 4, p. 411-414Conference paper, Published paper (Refereed)
    Abstract [en]

    A strategy that aims at relaxing the design of the clock network in digital circuits is evaluated through simulations and measurements on a test circuit. In the strategy a clock with long rise and fall times is used in conjunction with a D flip-flop that operates well with this clock. The test circuit consists of a digital FIR filter and a clock buffer with adjustable driving strength. It was designed and manufactured in a 0.35 μm CMOS process. The energy dissipation of the circuit increased 14% when the rise and fall times of the clock increased from 0.5 ns to 10 ns. The corresponding increase in propagation delay was less than 0.5 ns, i.e. an increase of 50% in propagation delay of the register. The results in this paper show that the clocking strategy can be implemented with low costs of power and speed.

    Keywords
    CMOS logic circuits, FIR filters, clocks, delays, flip-flops
    National Category
    Other Electrical Engineering, Electronic Engineering, Information Engineering
    Identifiers
    urn:nbn:se:liu:diva-14444 (URN)10.1109/TENCON.2004.1414957 (DOI)0-7803-8560-8 (ISBN)
    Available from: 2007-05-22 Created: 2007-05-22 Last updated: 2023-09-05
    4. Reduction of simultaneous switching noise in digital circuits
    Open this publication in new window or tab >>Reduction of simultaneous switching noise in digital circuits
    2006 (English)In: Proc. 24th IEEE Norchip Conf., NORCHIP'06, 2006, p. 187-190Conference paper, Published paper (Refereed)
    Abstract [en]

    In this paper the authors present results from measurements on a test chip used to evaluate our method for reduction of substrate noise that originates from the clock in digital circuits. The authors use long rise and fall times of the clock signal and a D flip-flop that operates well with this clock. With this approach, smaller clock buffers can be used, which results in smaller current peaks on the power supply lines and therefore less switching noise. The measured substrate noise on the test chip was reduced by 20% and up to 54%. With optimized clock buffers this method has a potential of an even larger noise reduction.

    Keywords
    CMOS integrated circuits, buffer circuits, clocks, flip-flops, integrated circuit noise, integrated circuit testing
    National Category
    Other Electrical Engineering, Electronic Engineering, Information Engineering
    Identifiers
    urn:nbn:se:liu:diva-14445 (URN)10.1109/NORCHP.2006.329207 (DOI)1-4244-0772-9 (ISBN)
    Available from: 2007-05-22 Created: 2007-05-22 Last updated: 2009-10-14
    5. Effect of simultaneous switching noise on an analog filter
    Open this publication in new window or tab >>Effect of simultaneous switching noise on an analog filter
    2006 (English)In: Proc. Int. Conf. on Electronics, Circuits and Systems, ICECS'06, 2006, p. 898-901Conference paper, Published paper (Refereed)
    Abstract [en]

    In this work a digital filter is placed on the same chip as an analog filter. We investigate how the simultaneous switching noise is propagated from the digital filter to different nodes on a manufactured chip. Conventional substrate noise reduction methods are used, e.g., separate power supplies, guard rings, and multiple pins for power supplies. We also investigate if the effect of substrate noise on the analog filter can be reduced by using a noise reduction method, which use long rise and fall times of the digital clock. The measured noise on the output of the analog filter was reduced by 30% up to 50% when the method was used.

    Keywords
    clocks, digital filters, integrated circuit noise, mixed analog-digital integrated circuits
    National Category
    Other Electrical Engineering, Electronic Engineering, Information Engineering
    Identifiers
    urn:nbn:se:liu:diva-14446 (URN)10.1109/ICECS.2006.379934 (DOI)1-4244-0395-2 (ISBN)
    Available from: 2007-05-22 Created: 2007-05-22 Last updated: 2009-10-14
    6. Introduction to substrate noise in SOI CMOS integrated circuits
    Open this publication in new window or tab >>Introduction to substrate noise in SOI CMOS integrated circuits
    2005 (English)In: Proc. National Conf. on Radio Science, RVK'05, 2005Conference paper, Published paper (Other academic)
    Abstract [en]

    In this paper an introduction to substrate noise in silicon oninsulator (SOI) is given. Differences between substratenoise coupling in conventional bulk CMOS and SOICMOS are discussed and analyzed by simulations. The efficiencyof common substrate noise reduction methods arealso analyzed. Simulation results show that the advantageof the substrate isolation in SOI is only valid up to a frequencythat highly depends on the chip structure. In bulk,guard bands are normally directly connected to the substrate.In SOI, the guard bands are coupled to the substratevia the parasitic capacitance of the silicon oxide. Therefore,the efficiency of a guard may be much larger in aconventional bulk than in SOI. One opportunity in SOI isthat a much higher resistivity of the substrate can be used,which results in a significantly higher impedance up to afrequency where the coupling is dominated by the capacitivecoupling of the substrate.

    National Category
    Other Electrical Engineering, Electronic Engineering, Information Engineering
    Identifiers
    urn:nbn:se:liu:diva-14447 (URN)
    Available from: 2007-05-22 Created: 2007-05-22 Last updated: 2023-09-05
    7. Programmable reference generator for on-chip measurement
    Open this publication in new window or tab >>Programmable reference generator for on-chip measurement
    2006 (English)In: Proc. 24th IEEE Norchip Conf., NORCHIP'06, 2006, p. 89-92Conference paper, Published paper (Refereed)
    Abstract [en]

    In this work, circuits for on-chip measurement and periodic waveform capture are designed. The aim is to analyze disturbances in mixed-signal chips such as simultaneous switching noise and the transfer of substrate noise. A programmable reference generator that replaces the standard digital-to-analog converter is proposed. It is based on a resistor string that is connected in a circular structure. A feature is that the reference outputs to the different comparators in the measurement channels are distributed over the nodes of the resistor string. Comparing with using a complete digital-to-analog converter, the use of a buffer is avoided. Hence, there is a potential reduction in the parasitic capacitance and power consumption as well as an increase in speed. We present results from a test chip demonstrating that simultaneous switching noise can be measured with the presented approach.

    Keywords
    comparators, digital-analog conversion, electric noise measurement, integrated circuit measurement, integrated circuit noise, programmable circuits, reference circuits
    National Category
    Other Electrical Engineering, Electronic Engineering, Information Engineering
    Identifiers
    urn:nbn:se:liu:diva-14448 (URN)10.1109/NORCHP.2006.329251 (DOI)1-4244-0772-9 (ISBN)
    Available from: 2007-05-22 Created: 2007-05-22 Last updated: 2023-09-05
    8. Reduction of simultaneous switching noise in analog signal band
    Open this publication in new window or tab >>Reduction of simultaneous switching noise in analog signal band
    2007 (English)In: Proc. IEEE European Conf. Circuit Theory and Design, ECCTD'07, 2007, p. 148-151Conference paper, Published paper (Refereed)
    Abstract [en]

    In this work we focus on reducing the simultaneous switching noise located in the frequency band from DC up to half of the digital clock frequency. This frequency band is assumed to be the signal band of an analog circuit. The idea is to use circuits that have as periodic power supply currents as possible to obtain low simultaneous switching noise below the clock in the frequency domain. We use precharged differential cascode switch logic together with a novel D flip-flop. To evaluate the method two pipelined adders have been implemented on transistor level in a 0.13 mum CMOS technology, where the novel circuit is implemented with our method and the reference circuit with static CMOS logic together with a TSPC D flip-flop. According to simulation results, the frequency components in the analog signal band can be attenuated from 10 dB up to 17 dB when using the proposed method. The cost is an increase in power consumption of almost a factor of three and a higher transistor count.

    Keywords
    CMOS integrated circuits, adders, flip-flops, frequency-domain analysis, mixed analog-digital integrated circuits, analog signal band, digital clock frequency, frequency components, frequency domain, higher transistor count, pipelined adders, precharged differential cascode switch logic, static CMOS logic, switching noise reduction, transistor level
    National Category
    Other Electrical Engineering, Electronic Engineering, Information Engineering
    Identifiers
    urn:nbn:se:liu:diva-14449 (URN)10.1109/ECCTD.2007.4529558 (DOI)978-1-4244-1341-6 (ISBN)
    Available from: 2007-05-22 Created: 2007-05-22 Last updated: 2009-10-14
    9. Bidirectional Conversion to Minimum Signed-Digit Representation
    Open this publication in new window or tab >>Bidirectional Conversion to Minimum Signed-Digit Representation
    2006 (English)In: Circuits and Systems, 2006. ISCAS 2006., 2006Conference paper, Published paper (Other academic)
    Abstract [en]

    In this work an approach to converting a number in two's complement representation to a minimum signed-digit representation is proposed. The novelty in this work is that this conversion is done from left-to-right and right-to-left concurrently. Hence, the execution time is significantly decreased, while the area overhead is small.

    Keywords
    Boolean functions, digital arithmetic, bidirectional conversion, signed-digit representation
    National Category
    Engineering and Technology
    Identifiers
    urn:nbn:se:liu:diva-14450 (URN)10.1109/ISCAS.2006.1693109 (DOI)
    Available from: 2007-05-22 Created: 2007-05-22 Last updated: 2015-03-11
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    FULLTEXT01
  • 108.
    Backenius, Erik
    et al.
    Linköping University, Department of Electrical Engineering, Electronics System.
    Säll, Erik
    Linköping University, Department of Electrical Engineering, Electronics System.
    Andersson, Ola
    Vesterbacka, Mark
    Linköping University, Department of Electrical Engineering, Electronics System.
    Programmable reference generator for on-chip measurement2006In: Proc. 24th IEEE Norchip Conf., NORCHIP'06, 2006, p. 89-92Conference paper (Refereed)
    Abstract [en]

    In this work, circuits for on-chip measurement and periodic waveform capture are designed. The aim is to analyze disturbances in mixed-signal chips such as simultaneous switching noise and the transfer of substrate noise. A programmable reference generator that replaces the standard digital-to-analog converter is proposed. It is based on a resistor string that is connected in a circular structure. A feature is that the reference outputs to the different comparators in the measurement channels are distributed over the nodes of the resistor string. Comparing with using a complete digital-to-analog converter, the use of a buffer is avoided. Hence, there is a potential reduction in the parasitic capacitance and power consumption as well as an increase in speed. We present results from a test chip demonstrating that simultaneous switching noise can be measured with the presented approach.

  • 109.
    Backenius, Erik
    et al.
    Linköping University, Department of Electrical Engineering.
    Vesterbacka, Mark
    Linköping University, Department of Electrical Engineering. Linköping University, Department of Electrical Engineering, Electronics System.
    A digital circuit with relaxed clocking2004In: Proc. Swedish System-on-Chip Conf., SSoCC'04, 2004Conference paper (Other academic)
    Abstract [en]

    A clock with adjustable rise and fall time is used in conjunction with a D flip-flop that operates well with this clock. Its intended use is to relax the design of the clock network in digital circuits and to alleviate the problems with simultaneous switching noise in mixed-signal circuits. A test chip has been designed in a 0.35 μm CMOS process. The chip consists of a clock driver with adjustable rise and fall times, and an FIR filter that uses the special D flip-flop in the registers. According to measurements, the digital circuit works well when the rise and fall times of the clock is varied from 0.5 ns to 10 ns. This makes the propagation delay in the critical path to vary between 13.0 ns and 13.7 ns, and the energy dissipation to vary between 1.5 pJ and 1.7 pJ, for an input signal with a transition activity of 0.4.

  • 110.
    Backenius, Erik
    et al.
    Linköping University, Department of Electrical Engineering, Electronics System.
    Vesterbacka, Mark
    Linköping University, Department of Electrical Engineering, Electronics System.
    Characteristics of a differential D flip-flop2003In: Proc. Swedish System-on-Chip Conf., SSoCC'03, 2003, Vol. 4Conference paper (Other academic)
    Abstract [en]

    A D flip-flop circuit that works well with long rise and fall times of the clock is characterized. This property is important when we would like to, e.g., relax the constraints on the clock distribution network or reduce the amount of noise generated in a mixed-signal circuit. Since the use of the D flip-flop allows small clock driver circuits, the amount of simultaneous switching noise can be reduced. There is also a potential for power savings with the use of smaller drivers, assuming that the short-circuit current in the flip-flops can be kept low. Moreover, the high frequency content of the clock is reduced, causing the noise that is injected into the substrate to be more easy to suppress. This is important in a mixed-signal circuit where analog circuits are present on the same substrate. The effects of long rise and fall times on the differential D flip-flop used in this work are mainly longer propagation times.

  • 111.
    Backenius, Erik
    et al.
    Linköping University, Department of Electrical Engineering, Electronics System.
    Vesterbacka, Mark
    Linköping University, Department of Electrical Engineering, Electronics System.
    Design of circuits for a robust clocking scheme2004In: Proc. 12th Mediterranean Electrotechnical Conf., MELECON'04, 2004, Vol. 1, p. 185-188Conference paper (Refereed)
    Abstract [en]

    The design of a clock distribution network in a digital integrated circuit is challenging in terms of obtaining low power consumption, low waveform degradation, low clock skew and low simultaneous switching noise. In this work we aim at alleviating these design restrictions by using a clock buffer with reduced size and a D flip-flop circuit with relaxed constraints on the rise and fall times of the clock. According to simulations the energy dissipation of a D flip-flop, implemented in a 0.35 μm process, increases with only 21% when the fall time of the clock is increased from 0.05 ns to 7.0 ns. Considering that smaller clock buffers can be used there is a potential of power savings by using the suggested clocking scheme.

  • 112.
    Backenius, Erik
    et al.
    Linköping University, Department of Electrical Engineering, Electronics System.
    Vesterbacka, Mark
    Linköping University, Department of Electrical Engineering, Electronics System.
    Evaluation of a clocking strategy with relaxed constraints on clock edges2004In: Proc. TENCON'04, 2004, Vol. 4, p. 411-414Conference paper (Refereed)
    Abstract [en]

    A strategy that aims at relaxing the design of the clock network in digital circuits is evaluated through simulations and measurements on a test circuit. In the strategy a clock with long rise and fall times is used in conjunction with a D flip-flop that operates well with this clock. The test circuit consists of a digital FIR filter and a clock buffer with adjustable driving strength. It was designed and manufactured in a 0.35 μm CMOS process. The energy dissipation of the circuit increased 14% when the rise and fall times of the clock increased from 0.5 ns to 10 ns. The corresponding increase in propagation delay was less than 0.5 ns, i.e. an increase of 50% in propagation delay of the register. The results in this paper show that the clocking strategy can be implemented with low costs of power and speed.

  • 113.
    Backenius, Erik
    et al.
    Linköping University, Department of Electrical Engineering, Electronics System.
    Vesterbacka, Mark
    Linköping University, Department of Electrical Engineering, Electronics System.
    Introduction to substrate noise in SOI CMOS integrated circuits2005In: Proc. National Conf. on Radio Science, RVK'05, 2005Conference paper (Other academic)
    Abstract [en]

    In this paper an introduction to substrate noise in silicon oninsulator (SOI) is given. Differences between substratenoise coupling in conventional bulk CMOS and SOICMOS are discussed and analyzed by simulations. The efficiencyof common substrate noise reduction methods arealso analyzed. Simulation results show that the advantageof the substrate isolation in SOI is only valid up to a frequencythat highly depends on the chip structure. In bulk,guard bands are normally directly connected to the substrate.In SOI, the guard bands are coupled to the substratevia the parasitic capacitance of the silicon oxide. Therefore,the efficiency of a guard may be much larger in aconventional bulk than in SOI. One opportunity in SOI isthat a much higher resistivity of the substrate can be used,which results in a significantly higher impedance up to afrequency where the coupling is dominated by the capacitivecoupling of the substrate.

  • 114.
    Backenius, Erik
    et al.
    Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Electronics System.
    Vesterbacka, Mark
    Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Electronics System.
    Pin assignment for low simultaneous switching noise2005In: Proc. Swedish System-on-Chip Conf., SSoCC'05, 2005Conference paper (Other academic)
    Abstract [en]

    Simultaneous switching noise (SSN) can degrade the performance of digital circuits. In mixed-signal circuits, the performance of analog circuits are degraded by the SSN that is spread from digital circuits through the substrate to the analog circuits. The most critical parameter when considering SSN is the parasitic inductance in the power supply path from off-chip to on-chip. In this paper, basic theories of inductance of current paths are given for parallel interconnects throughout examples. The results from these examples show that the placement of interconnects plays a big role for the effective inductance. Power supply interconnects should be placed with small distances in between, and so that currents in adjacent interconnects are in opposite directions. With this strategy, a low inductance in the power supply current path can be achieved. The importance of choosing a good package for the silicon die is also briefly discussed.

  • 115.
    Backenius, Erik
    et al.
    Linköping University, Department of Electrical Engineering, Electronics System.
    Vesterbacka, Mark
    Linköping University, Department of Electrical Engineering, Electronics System.
    Reduction of simultaneous switching noise in digital circuits2006In: Proc. 24th IEEE Norchip Conf., NORCHIP'06, 2006, p. 187-190Conference paper (Refereed)
    Abstract [en]

    In this paper the authors present results from measurements on a test chip used to evaluate our method for reduction of substrate noise that originates from the clock in digital circuits. The authors use long rise and fall times of the clock signal and a D flip-flop that operates well with this clock. With this approach, smaller clock buffers can be used, which results in smaller current peaks on the power supply lines and therefore less switching noise. The measured substrate noise on the test chip was reduced by 20% and up to 54%. With optimized clock buffers this method has a potential of an even larger noise reduction.

  • 116.
    Backenius, Erik
    et al.
    Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
    Vesterbacka, Mark
    Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
    Hägglund, Robert
    Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
    A strategy for reducing clock noise in mixed-signal circuits2002In: Proc. IEEE 45th Midwest Symp. on Circuits and Systems, MWSCAS'02, 2002, Vol. 1, p. 29-32Conference paper (Refereed)
    Abstract [en]

    Digital switching noise is of major concern in mixed-signal circuits due to the coupling of the noise via a shared substrate to the analog circuits. A significant noise source in this context is the digital clock network that generally has a high switching activity. There is a large capacitive coupling between the clock network and the substrate. Switching of the clock produces current peaks causing simultaneous switching noise (SSN). Sharp clock edges yields a high frequency content of the clock signal and a large SSN. High frequency noise is less attenuated through the substrate than low frequencies due to the parasitic inductance of the interconnect from on-chip to off-chip. In this work, we present a strategy that targets the problems with clock noise. The approach is to generate a clock with smooth edges, i.e. reducing both the high frequency components of the clock signal and the current peaks produced in the power supply. We use a special digital D flip-flop circuit that operates well with the clock. A test chip has been designed where we can control the rise and fall time of the clock edges in a digital FIR filter, and measure the performance of a fifth-order analog active-RC filter.

  • 117.
    Backenius, Erik
    et al.
    Linköping University, Department of Electrical Engineering, Electronics System.
    Vesterbacka, Mark
    Linköping University, Department of Electrical Engineering, Electronics System.
    Hägglund, Robert
    Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
    Effect of simultaneous switching noise on an analog filter2006In: Proc. Int. Conf. on Electronics, Circuits and Systems, ICECS'06, 2006, p. 898-901Conference paper (Refereed)
    Abstract [en]

    In this work a digital filter is placed on the same chip as an analog filter. We investigate how the simultaneous switching noise is propagated from the digital filter to different nodes on a manufactured chip. Conventional substrate noise reduction methods are used, e.g., separate power supplies, guard rings, and multiple pins for power supplies. We also investigate if the effect of substrate noise on the analog filter can be reduced by using a noise reduction method, which use long rise and fall times of the digital clock. The measured noise on the output of the analog filter was reduced by 30% up to 50% when the method was used.

  • 118.
    Backenius, Erik
    et al.
    Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
    Vesterbacka, Mark
    Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
    Hägglund, Robert
    Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
    Reduction of Clock Noise in Mixed-Signal Circuits2002In: Proc. National Conf. on Radio Science, RVK'02, 2002, Vol. 1, p. 197-201Conference paper (Other academic)
    Abstract [en]

    A major concern in mixed-signal circuits is the noise injected by the digital circuits into sensitive analog circuits. Of particular interest in this work is the problem with large capacitive coupling between the digital clock network and the substrate shared with the analog circuits. It is in general more easy to reduce low frequency noise compared with high frequency noise. Therefore, we have developed a strategy where we reduce the high frequency content of the clock by using smooth clock edges, and a special digital flip-flop circuit. This strategy will be evaluated in a test chip where we can control the rise and fall time of the clock edges of a high-performance digital FIR filter, and measure the performance of a fifth-order analog active-RC filter.

  • 119.
    Backenius, Erik
    et al.
    Linköping University, Department of Electrical Engineering, Electronics System.
    Vesterbacka, Mark
    Linköping University, Department of Electrical Engineering, Electronics System.
    Settu, V.B.
    Linköping University, Department of Electrical Engineering. Linköping University, The Institute of Technology.
    Reduction of simultaneous switching noise in analog signal band2007In: Proc. IEEE European Conf. Circuit Theory and Design, ECCTD'07, 2007, p. 148-151Conference paper (Refereed)
    Abstract [en]

    In this work we focus on reducing the simultaneous switching noise located in the frequency band from DC up to half of the digital clock frequency. This frequency band is assumed to be the signal band of an analog circuit. The idea is to use circuits that have as periodic power supply currents as possible to obtain low simultaneous switching noise below the clock in the frequency domain. We use precharged differential cascode switch logic together with a novel D flip-flop. To evaluate the method two pipelined adders have been implemented on transistor level in a 0.13 mum CMOS technology, where the novel circuit is implemented with our method and the reference circuit with static CMOS logic together with a TSPC D flip-flop. According to simulation results, the frequency components in the analog signal band can be attenuated from 10 dB up to 17 dB when using the proposed method. The cost is an increase in power consumption of almost a factor of three and a higher transistor count.

  • 120.
    Backskär, Daniel
    Linköping University, Department of Electrical Engineering.
    Beskrivning av systemfunktioner i kärnkraftverk med hjälp av objektorienterat modelleringsverktyg2002Independent thesis Basic level (professional degree)Student thesis
    Abstract [en]

    In order to facilitate design and maintenance of such a large and complex site as a nuclear power plant, all system functions must be described in a stringent way. In the past, these descriptions consisted of text documents and logical diagrams, but today there are an increasing number of object-oriented programs available on the market which might be used for this purpose. This Master Thesis has made a closer study of one of these programs named Rational Rose. The principal of the program is to facilitate software design and development, not to create models of plants. However, using the program the same way as developing software, specifying actors then gradually extend the model with use cases, use cases diagrams etc, the same methods can be used when modelling plants.

    During this Master Thesis most of the time has been spent developing, structuring and classifying the functions composing the Feed Water Backup System of the reactor named Oskarshamn 3. A considerable amount of time was also spent to find a general structure for typical motor and valve circuits in the plant, which are also applicable for the configuration of the Feed Water Backup System. This general structure will then be used to support maintenance and to get faster decisions when new systems are designed.

    Effectuating the modernization of the nuclear power plants in Sweden, an ever- increasing use of highly software intensive systems will be introduced, which also leads to the need of finding other ways to describe those systems. A suitable method is to use Rational Rose, where the entire process, from description to final product, will be done in an integrated way. Use cases are generated and together with their related documentation they will form the description of the desired system functions.

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  • 121.
    Backström, Anders
    et al.
    Linköping University, Department of Science and Technology.
    Ågesjö, Mats
    Linköping University, Department of Science and Technology.
    Design and implementation of a 5GHz radio front-end module2004Independent thesis Basic level (professional degree)Student thesis
    Abstract [en]

    The overall goal of this diploma work is to produce a design of a 5 GHz radio frontend using Agilent Advanced Design System (ADS) and then build a working prototype. Using this prototype to determine if RF circuits at 5 GHz can be successfully produced using distributed components on a laminate substrate.

    The design process for the radio front-end consists of two stages. In the first stage the distributed components are designed and simulated, and in the second stage all components are merged into a PCB. This PCB is then manufactured and assembled. All measurements on the radio front-end and the test components are made using a network analyser, in order to measure the S-parameters.

    This diploma work has resulted in a functional design and prototype, which has proved that designing systems for 5 GHz on a laminate substrate is possible but by no means trivial.

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  • 122.
    Baer, Donald R.
    et al.
    Pacific Northwest Natl Lab, WA 99352 USA.
    Artyushkova, Kateryna
    Phys Elect, MN 55317 USA.
    Cohen, Hagai
    Weizmann Inst Sci, Israel.
    Easton, Christopher D.
    CSIRO Mfg, Australia.
    Engelhard, Mark
    Pacific Northwest Natl Lab, WA 99352 USA.
    Gengenbach, Thomas R.
    CSIRO Mfg, Australia.
    Greczynski, Grzegorz
    Linköping University, Department of Physics, Chemistry and Biology, Thin Film Physics. Linköping University, Faculty of Science & Engineering.
    Mack, Paul
    Thermo Fisher Sci, England.
    Morgan, David J.
    Cardiff Univ, Wales.
    Roberts, Adam
    Kratos Analyt Ltd, England.
    XPS guide: Charge neutralization and binding energy referencing for insulating samples2020In: Journal of Vacuum Science & Technology. A. Vacuum, Surfaces, and Films, ISSN 0734-2101, E-ISSN 1520-8559, Vol. 38, no 3Article in journal (Refereed)
    Abstract [en]

    This guide deals with methods to control surface charging during XPS analysis of insulating samples and approaches to extracting useful binding energy information. The guide summarizes the causes of surface charging, how to recognize when it occurs, approaches to minimize charge buildup, and methods used to adjust or correct XPS photoelectron binding energies when charge control systems are used. There are multiple ways to control surface charge buildup during XPS measurements, and examples of systems on advanced XPS instruments are described. There is no single, simple, and foolproof way to extract binding energies on insulating material, but advantages and limitations of several approaches are described. Because of the variety of approaches and limitations of each, it is critical for researchers to accurately describe the procedures that have been applied in research reports and publications.

  • 123.
    Bahaghighat, Mahdi
    et al.
    Imam Khomeini Int Univ, Iran.
    Abedini, Fereshteh
    Linköping University, Department of Science and Technology, Media and Information Technology. Linköping University, Faculty of Science & Engineering. Amirkabir Univ Technol, Iran.
    Xin, Qin
    Univ Faroe Isl, Faroe Islands.
    Zanjireh, Morteza Mohammadi
    Imam Khomeini Int Univ, Iran.
    Mirjalili, Seyedali
    Torrens Univ Australia, Australia; Yonsei Univ, South Korea.
    Using machine learning and computer vision to estimate the angular velocity of wind turbines in smart grids remotely2021In: Energy Reports, E-ISSN 2352-4847, Vol. 7, p. 8561-8576Article in journal (Refereed)
    Abstract [en]

    Today, power generation from clean and renewable resources such as wind and solar is of great salience. Smart grid technology efficiently responds to the increasing demand for electric power. Intelligent monitoring, control, and maintenance of wind energy facilities are indispensable to increase the performance and efficiency of smart grids (SGs). Integration of state-of-the-art machine learning algorithms and vision sensor networks approaches pave the way toward enhancing the wind farms performance. The generating power in a wind turbine farm is the most critical parameter that should be measured accurately. Produced power is highly related to weather patterns, and a new farm in a near area is also likely to have similar energy generation. Therefore, accurate and perpetual prediction models of the existing wind farms can be led to develop new stations with lower costs. The paper aims to estimate the angular velocity of turbine blades using vision sensors and signal processing. The high wind in the wind farm can cause the camera to vibrate in successive frames, and the noise in the input images can also strengthen the problem. Thanks to couples of solid computer vision algorithms, including FAST (Features from Accelerated Segment Test), SIFT (Scale-Invariant Feature Transform), SURF (Speeded Up Robust Features), BF (Brute-Force), FLANN (Fast Library for Approximate Nearest Neighbors), AE (Autoencoder), and SVM (support vector machines), this paper accurately localizes the Hub and track the presence of the Blade in consecutive frames of a video stream. The simulation results show that determining the hub location and the blade presence in sequential frames results in an accurate estimation of wind turbine angular velocity with 95.36% accuracy. (C) 2021 The Authors. Published by Elsevier Ltd.

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  • 124.
    Baig, Aijaz
    Linköping University, Department of Computer and Information Science.
    Embedded boundary scan for test & debug2009Independent thesis Advanced level (degree of Master (Two Years)), 20 credits / 30 HE creditsStudent thesis
    Abstract [en]

    The boundary scan standard which has been in existence since the early nineties is widely used to test printed circuit boards (PCB). It is primarily aimed at providing increased physical test access to surface mounted devices on printed circuit boards (PCB). Using boundary scan avoids using functional testing and In-circuit-techniques like 'bed of nails' for structurally testing PCBs as increasing densities and complexities made opting for them a herculean task. Though the standard has had a revolutionizing effect on board testing conducted during the development and production phases, there is a lack of a standardized mechanism to allow IEEE 1149.1 to be used in a system post installation. This has led to problems typically encountered during field test runs, like the issue of high number of No-Fault-Found (NFF), being left unaddressed. The solution lies in conducting a structural test after a given module has already been installed in the system. This can be done by embedding the programmability features of the boundary scan test mechanism into the Unit under test (UUT) thereby enabling the UUT to conduct boundary scan based self tests without the need of external stimuli. In this thesis, a test and debug framework, which aims to use boundary-scan in post system-installation, is the subject of a study and subsequent enhancement. The framework allows embedding much of the test vector deployment and debug mechanism onto the Unit under test (UUT) to enable its remote testing and debug. The framework mainly consists of a prototype board which, along with the UUT, comprise the 'embedded system'. The following document is a description of the phased development of above said framework and its intended usage in the field.

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  • 125.
    Bajramovic, Jasko
    Linköping University, Department of Electrical Engineering.
    FPGA Implementation of an Interpolator for PWM applications2007Independent thesis Basic level (professional degree), 20 points / 30 hpStudent thesis
    Abstract [en]

    In this thesis, a multirate realization of an interpolation operation is explored. As one of the requirements for proper functionality of the digital pulse-width modulator, a 16-bit digital input signal is to be upsampled 32 times. To obtain the required oversampling ratio, five separate interpolator stages were designed and implemented. Each interpolator stage performed uppsampling by a factor of two followed by an image-rejection lowpass FIR filter. Since, each individual interpolator stage upsamples the input signal by a factor of two, interpolation filters were realized as a half-band FIR filters. This kind of linear-phase FIR filters have a nice property of having every other filter coefficient equal to zero except for the middle one which equals 0.5. By utilizing the half-band FIR filters for the actual realization of the interpolation filters, the overall computational complexity was substantially reduced. In addition, several multirate techniques have been utilized for deriving more efficient interpolator structures. Hence, the impulse response of individual interpolator filters was rewritten into its corresponding polyphase form. This further simplifies the interpolator realization. To eliminate multiplication by 0.5 in one of two polyphase subfilters, the filter gain was deliberately increased by a factor of two. Thus, one polyphase path only contained delay elements. In addition, for the realization of filter multipliers, a multiple constant multiplication, (MCM), algorithm was utilized. The idea behind the MCM algorithm, was to perform multiplication operations as a number of addition operations and appropriate input signal shifts. As a result, less hardware was needed for the actual interpolation chain implementation. For the correct functionality of the interpolator chain, scaling coefficients were introduced into the each interpolation stage. This is done in order to reduce the possibility of overflow. For the scaling process, a safe scaling method was used. The actual quantization noise generated by the interpolator chain was also estimated and appropriate system adjustments were performed.

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  • 126.
    Bajramovic, Jasko
    Linköping University, Department of Electrical Engineering.
    Implementation of a multirate IIR filter2003Independent thesis Basic level (professional degree)Student thesis
    Abstract [en]

    In this report a two-stage multirate IIR filter has been modelled and simulated in the Simulink. For its realization, the multirate structure for narrow-band and middle-band filters and the multirate structure for the wide- band filters have been used. In Simulink, the different filter elements within the two-stage multirate IIR filter have been modelled separately and subsequently they have been interconnected into the two-stage multirate structure. This overall two-stage multirate IIR filter makes use of half-band FIR filters to alter the sampling frequency, an IIR filter for the actual filtering and allpass filters to construct complementary filters. Once the two- stage multirate IIR filter has been designed, the scaling coefficients have been introduced into the filter structure. The same filter specifications as that used for the multirate IIR filter designing were also used for the singlerate IIR filter modelling. Simulink was used for the simulation of the singlerate IIR filter, as well. When designed, the singlerate IIR filter has been used as a reference filter for the determination of the roundoff noise and the data word length of the multirate IIR filter. One aspect found is that the roundoff noise of the multirate IIR filter is slightly larger than that obtained by a singlerate IIR filter.

  • 127. Order onlineBuy this publication >>
    Balachandran, Arvind
    Linköping University, Department of Electrical Engineering, Vehicular Systems. Linköping University, Faculty of Science & Engineering.
    Battery Integrated Modular Multilevel Converter Topologies for Automotive Applications2023Licentiate thesis, comprehensive summary (Other academic)
    Abstract [en]

    Electric vehicles are rapidly developing in response to the need for increasing sustainable energy sources. The range and lifetime of an electric vehicle are limited by the battery pack. A pack comprises modules with several parallel and/or series-connected cells. Differences in leakage currents and cell in-homogeneities cause individual cell voltage and state-of-charge distribution among the cells to be non-homogeneous. As a result, over time, some cells discharge faster than other cells, thus limiting the total energy delivered by the pack. In order to maximize the energy delivered by the pack, individual cell control is desirable. As a solution, battery-integrated modular multi-level converter (BI-MMC) topologies are proposed, presented, and evaluated. BI-MMC topology consists of either one or two arms per phase, and each arm comprises several cascaded stages of DC–AC converters and is commonly referred to as submodules. BI-MMCs provide increased controllability and potential improvement in the lifetime of the battery pack. Furthermore, BI-MMCs have low output total harmonic distortion, further improving the powertrain efficiency.

    The first contribution is the design and evaluation of 3-phase and 6-phase BI-MMCs; comparisons are made against a conventional 2-level inverter for a 40-ton 400 kW commercial vehicle. The evaluation considers the total number of submodules, energy rating of the DC-link capacitors, battery losses, capacitor losses, and semiconductor losses. The evaluation showed that the BI-MMCs have lower semiconductor losses than the conventional 2-level inverter. However, the BI-MMCs have higher capacitor and battery losses. The second contribution is the investigation of the impact that the number of series connected cells per submodule has on the total losses of the BI-MMC. The study showed that 5- to 6-series connected cells have the lowest losses. The third contribution is the design principles for optimization of the DC-link capacitors and the MOSFET switching frequency; this is supported by experimental validation for the loss distribution within a submodule. The fourth contribution is a methodology for determining the battery impedance using the full-load converter current. In a conventional battery pack, the battery is connected directly to the fast charger’s DC supply. However, in a BI-MMC, the battery and the inverter are integrated, potentially increasing the DC charging capabilities because higher voltages can be achieved during charging than during operation. The fifth contribution is thus the derivation and investigation of the maximum DC charging power of BI-MMCs assuming the same submodule semiconductor losses during traction. The analysis showed that most BI-MMCs have a maximum DC charging power of about 1MW.

    List of papers
    1. Design and Analysis of Battery-Integrated Modular Multilevel Converters for Automotive Powertrain Applications
    Open this publication in new window or tab >>Design and Analysis of Battery-Integrated Modular Multilevel Converters for Automotive Powertrain Applications
    2021 (English)In: 2021 23RD EUROPEAN CONFERENCE ON POWER ELECTRONICS AND APPLICATIONS (EPE21 ECCE EUROPE), IEEE , 2021Conference paper, Published paper (Refereed)
    Abstract [en]

    The automotive industry has grown considerably over the last century consequently increasing green-house gas emissions and thus contributing towards increase in the average global temperature. It is thus of paramount importance to increase the use of alternative energy sources. Electric vehicles have gained popularity over the last decade. However, a major concern with electric vehicles is their range. The range of an electric vehicle is limited by the battery pack, in particular, the weakest cell of the pack. One method of increasing the available energy from the battery pack is by introducing more electronics. Modular multilevel converters, with their modular concept, could be a viable solution. The concept of battery-integrated modular multilevel converters (BI-MMC) for automotive applications is explored. In particular, the impact of the number of cascaded cells per submodule is investigated, considering battery losses, DC-link capacitor losses, and the converter losses. Furthermore, an optimization of the DC-link capacitors and the selection of MOSFET switching frequency is presented in order to minimize the total losses.

    Place, publisher, year, edition, pages
    IEEE, 2021
    Series
    European Conference on Power Electronics and Applications, ISSN 2325-0313
    Keywords
    DC-AC converters, Modular Multilevel Converters, Power converters for EV, Electric vehicle, Hybrid Electric Vehicle (HEV)
    National Category
    Other Electrical Engineering, Electronic Engineering, Information Engineering
    Identifiers
    urn:nbn:se:liu:diva-187241 (URN)10.23919/EPE21ECCEEurope50061.2021.9570570 (DOI)000832143901075 ()9789075815375 (ISBN)9781665433846 (ISBN)
    Conference
    23rd European Conference on Power Electronics and Applications (EPE ECCE Europe), ELECTR NETWORK, sep 06-10, 2021
    Available from: 2022-08-15 Created: 2022-08-15 Last updated: 2023-09-19
    2. Experimental Evaluation of Battery Impedance and Submodule Loss Distribution for Battery Integrated Modular Multilevel Converters
    Open this publication in new window or tab >>Experimental Evaluation of Battery Impedance and Submodule Loss Distribution for Battery Integrated Modular Multilevel Converters
    2022 (English)In: 2022 24TH EUROPEAN CONFERENCE ON POWER ELECTRONICS AND APPLICATIONS (EPE22 ECCE EUROPE), Institute of Electrical and Electronics Engineers (IEEE), 2022Conference paper, Published paper (Refereed)
    Abstract [en]

    Greenhouse gas emissions and the increase in average global temperature are growing concerns now more so than ever. Therefore it is of importance to increase the use of alternative energy sources, especially in the automotive industry. Battery electric vehicles (BEV) have gained popularity over the past several years. However, the performance of a BEV is limited by the battery pack, in particular, the weakest cell in the pack. Therefore, improved cell controllability and high efficiency are seen as important directions for research and development and one direction where it can be achieved is through using battery-integrated modular multilevel converters (BI-MMC). The battery current in BI-MMCs contains additional harmonics and the frequency dependent losses of these harmonics are determined by the resonance between the battery and the DC-link capacitor bank. The paper presents an experimental validation of previously published theoretical results for both harmonic allocations and loss distribution at the switching frequency within the BI-MMC submodule. Furthermore, a methodology for measuring the battery impedance using the full-load converter switching currents is presented.

    Place, publisher, year, edition, pages
    Institute of Electrical and Electronics Engineers (IEEE), 2022
    Series
    European Conference on Power Electronics and Applications, ISSN 2325-0313
    Keywords
    Modular Multilevel Converters (MMC); Power converters for EV; Batteries; DC-AC converters; Automotive application
    National Category
    Other Electrical Engineering, Electronic Engineering, Information Engineering
    Identifiers
    urn:nbn:se:liu:diva-187242 (URN)000886231600101 ()9789075815399 (ISBN)9781665487009 (ISBN)
    Conference
    24th European Conference on Power Electronics and Applications (EPE ECCE Europe), Hanover, GERMANY, sep 05-09, 2022
    Available from: 2022-08-15 Created: 2022-08-15 Last updated: 2023-10-12Bibliographically approved
    3. DC Charging Capabilities of Battery-Integrated Modular Multilevel Converters Based on Maximum Tractive Power
    Open this publication in new window or tab >>DC Charging Capabilities of Battery-Integrated Modular Multilevel Converters Based on Maximum Tractive Power
    2023 (English)In: Electricity, E-ISSN 2673-4826, Vol. 4, no 1, p. 62-77Article in journal (Refereed) Published
    Abstract [en]

    The increase in the average global temperature is a consequence of high greenhouse gas emissions. Therefore, using alternative energy carriers that can replace fossil fuels, especially for automotive applications, is of high importance. Introducing more electronics into an automotive battery pack provides more precise control and increases the available energy from the pack. Battery-integrated modular multilevel converters (BI-MMCs) have high efficiency, improved controllability, and better fault isolation capability. However, integrating the battery and inverter influences the maximum DC charging power. Therefore, the DC charging capabilities of 5 3-phase BI-MMCs for a 40-ton commercial vehicle designed for a maximum tractive power of 400 kW was investigated. Two continuous DC charging scenarios are considered for two cases: the first considers the total number of submodules during traction, and the second increases the total number of submodules to ensure a maximum DC charging voltage of 1250 V. The investigation shows that both DC charging scenarios have similar maximum power between 1 and 3 MW. Altering the number of submodules increases the maximum DC charging power at the cost of increased losses.

    Place, publisher, year, edition, pages
    MDPI, 2023
    Keywords
    EV powertrain; DC charging; batteries; DC-AC converters; MMC; BI-MMC; AC batteries; reconfigurable batteries; modular batteries
    National Category
    Energy Systems
    Identifiers
    urn:nbn:se:liu:diva-191802 (URN)10.3390/electricity4010005 (DOI)001187454500001 ()
    Note

    Funding Agencies|Foundation for Strategic Environmental Research (MISTRA)

    Available from: 2023-02-15 Created: 2023-02-15 Last updated: 2024-04-17Bibliographically approved
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  • 128.
    Balachandran, Arvind
    Linköping University, Department of Electrical Engineering, Integrated Circuits and Systems. arvindb316@gmail.com.
    Performance Evaluation of Modular Multilevel Converters for Photovoltaic Systems2019Independent thesis Advanced level (degree of Master (Two Years)), 20 credits / 30 HE creditsStudent thesis
    Abstract [en]

    Modular Multilevel Converters (MMCs), over recent years, have gained popularity in high-voltage(HV) and medium-voltage (MV) applications due to their high reliability. Also, with the rapid growth of solar photovoltaics (PV) and energy storage systems, there is a high demand for efficient and reliable power converter solutions. Therefore, due to the seen merits behind MMCs, this thesis assesses their performance for low-voltage (LV) applications. This is accomplished by comparing basic MMC solutions with an equivalent flying capacitors based solution. Such comparison is based on the evaluation of the passive elements requirements, semi-conductor losses, area, voltage, and current stresses, and common-mode voltage. It is worth mentioning that the evaluation is based on utilizing LV MOSFETs. Furthermore, the thesis introduces a modulation scheme for the full-bridge submodule MMC, thus further exploring the different operating regions of the full-bridge based MMC.

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  • 129.
    Balachandran, Arvind
    et al.
    Linköping University, Department of Electrical Engineering, Vehicular Systems. Linköping University, Faculty of Science & Engineering.
    Jonsson, Tomas
    Linköping University, Department of Electrical Engineering, Vehicular Systems. Linköping University, Faculty of Science & Engineering.
    Eriksson, Lars
    Linköping University, Department of Electrical Engineering, Vehicular Systems. Linköping University, Faculty of Science & Engineering.
    Design and Analysis of Battery-Integrated Modular Multilevel Converters for Automotive Powertrain Applications2021In: 2021 23RD EUROPEAN CONFERENCE ON POWER ELECTRONICS AND APPLICATIONS (EPE21 ECCE EUROPE), IEEE , 2021Conference paper (Refereed)
    Abstract [en]

    The automotive industry has grown considerably over the last century consequently increasing green-house gas emissions and thus contributing towards increase in the average global temperature. It is thus of paramount importance to increase the use of alternative energy sources. Electric vehicles have gained popularity over the last decade. However, a major concern with electric vehicles is their range. The range of an electric vehicle is limited by the battery pack, in particular, the weakest cell of the pack. One method of increasing the available energy from the battery pack is by introducing more electronics. Modular multilevel converters, with their modular concept, could be a viable solution. The concept of battery-integrated modular multilevel converters (BI-MMC) for automotive applications is explored. In particular, the impact of the number of cascaded cells per submodule is investigated, considering battery losses, DC-link capacitor losses, and the converter losses. Furthermore, an optimization of the DC-link capacitors and the selection of MOSFET switching frequency is presented in order to minimize the total losses.

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  • 130.
    Balachandran, Arvind
    et al.
    Linköping University, Department of Electrical Engineering, Vehicular Systems. Linköping University, Faculty of Science & Engineering.
    Jonsson, Tomas
    Linköping University, Department of Electrical Engineering, Vehicular Systems. Linköping University, Faculty of Science & Engineering. Scania, Södertalje, Sweden.
    Eriksson, Lars
    Linköping University, Department of Electrical Engineering, Vehicular Systems. Linköping University, Faculty of Science & Engineering.
    Larsson, Anders
    Scania, Södertalje, Sweden.
    Experimental Evaluation of Battery Impedance and Submodule Loss Distribution for Battery Integrated Modular Multilevel Converters2022In: 2022 24TH EUROPEAN CONFERENCE ON POWER ELECTRONICS AND APPLICATIONS (EPE22 ECCE EUROPE), Institute of Electrical and Electronics Engineers (IEEE), 2022Conference paper (Refereed)
    Abstract [en]

    Greenhouse gas emissions and the increase in average global temperature are growing concerns now more so than ever. Therefore it is of importance to increase the use of alternative energy sources, especially in the automotive industry. Battery electric vehicles (BEV) have gained popularity over the past several years. However, the performance of a BEV is limited by the battery pack, in particular, the weakest cell in the pack. Therefore, improved cell controllability and high efficiency are seen as important directions for research and development and one direction where it can be achieved is through using battery-integrated modular multilevel converters (BI-MMC). The battery current in BI-MMCs contains additional harmonics and the frequency dependent losses of these harmonics are determined by the resonance between the battery and the DC-link capacitor bank. The paper presents an experimental validation of previously published theoretical results for both harmonic allocations and loss distribution at the switching frequency within the BI-MMC submodule. Furthermore, a methodology for measuring the battery impedance using the full-load converter switching currents is presented.

    Download full text (pdf)
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  • 131.
    Balachandran, Arvind
    et al.
    Linköping University, Department of Electrical Engineering, Vehicular Systems. Linköping University, Faculty of Science & Engineering.
    Jonsson, Tomas Uno
    Linköping University, Department of Electrical Engineering, Vehicular Systems. Linköping University, Faculty of Science & Engineering.
    Eriksson, Lars
    Linköping University, Department of Electrical Engineering, Vehicular Systems. Linköping University, Faculty of Science & Engineering.
    Experimental Evaluation of Submodule Losses in Battery-Integrated MMCs with NLM and PSPWM2024Conference paper (Refereed)
    Abstract [en]

    Electric vehicle (EV) battery packs contain several parallel and series-connected cells and variations in leakage currents and cell characteristics result in heterogeneous discharge rates among cells, thus limiting the total energy delivery of the pack. Battery-integrated modular multilevel converters (BI-MMCs) increase the controllability of cells thereby improving the energy utilization of the battery pack. Design optimization for BI-MMC with phase-shifted modulation (PSPWM) showed that submodule (SM) DC-link capacitors designed to bypass the switching frequency components result in minimum total losses. However, this requires a large DC-link capacitor bank, which increases the system cost. An alternative modulation technique, nearest level modulation (NLM), characterized by low semiconductor switching frequency, is often preferred for MMCs with many SMs. The first contribution is an experimental loss comparison in an SM of a BI-MMC with PSPWM and NLM. The second contribution is investigating the impact of the size of DC-link capacitors on battery and capacitor losses for NLM. The experiments showed that the battery and capacitor losses are independent of the DC-link capacitor size when using NLM. Furthermore, NLM has lower total losses but higher battery losses than PSPWM. A single-phase 4-SM BI-MMC is used as the experimental platform for the comparison.

  • 132.
    Bandla, Atchaiah
    Linköping University, Department of Science and Technology, Physics and Electronics. Linköping University, The Institute of Technology.
    Highly Linear 2.45 GHz Low-Noise Amplifier Design2015Independent thesis Advanced level (degree of Master (Two Years)), 20 credits / 30 HE creditsStudent thesis
    Abstract [en]

    One critical component of the communication receiver of front-end system is the low-noise amplifier (LNA). For good sensitivity and dynamic range, the LNA should provide a low noise figure and maximum attainable power gain. Another concern is the linearity of the LNA. Strong signals produce intermodulation products in a frequency band close to the operating frequency that might affect the performance of the receiver. In many cases, the intermodulation products can be reduced by increasing the current through the active device. Hence, a trade-off between power consumption and linearity must be considered when designing the LNA. The thesis includes the bias network design, stability analysis, matching network design and layout design of the LNA RF module with layout simulation. The simulation has been performed using Advanced Design System (ADS) simulation software. After implementation of LNA on a PCB, the LNA is measured with the help of the power supply unit and vector network analyzer. The proposed design aim is to provide a low noise figure (NF) and high gain while maintaining the low power consumption.

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  • 133.
    Banerjee, Saptarshi
    Linköping University, Department of Electrical Engineering, Integrated Circuits and Systems.
    Power Supply Rejection (PSR) Enhancement Techniques for Fully Integrated Low-Dropout (LDO) Regulators2020Independent thesis Advanced level (degree of Master (Two Years)), 20 credits / 30 HE creditsStudent thesis
    Abstract [en]

    In this present world, there is a huge requirement of portable devices for that the analysis of low-dropout or LDO regulators have been on high priority. So, for every respective device, there is a power budget that acts as the main constraint to design an LDO. The LDO design aims to suppress the noise and supply noise-free or low noise output. This thesis paper illustrates several designs of output capacitor-less LDO architecture to enhance Power Supply Rejection (PSR) and optimization of the ideas from different literature to achieve the low quiescent current, stability with fast transient response while the input voltage is low over a wide range of load current. Differ-ent types of transistor schematic designs under definite specifications of the LDOs, which are mostly integrated by major components like Error Amplifier (EA) and pass transistor, feedback resistors, and relatively small output capacitor have mostly considered for the designs. However, some buffer attenuation techniques which can improve the PSR have also been shown with a proper diagram. The design of LDOwith the components and how to design the pass device and their trade off’s have been has been discussed. Different techniques of PSR enhancement among which some of the techniques have been implemented have been illustrated with respective diagrams. A study of executed techniques under the specifications with comparative results has been shown with their trade-off with the other architecture. The contribution is an LDO that has been simulated in Cadence specter and designed in CMOS FinFET process node atVdd= 0.95 V with a load current of 50 mA -75 mA and an output voltage of 0.75 V with a small output capacitor of 200 pF, a PSR of−25 dB at 100 MHz has been achieved whereas the current consumption at the load is 245μA, while meeting the targeted stability analysis of gain margin and phase margin of 47 dB and 63◦respectively. A small voltage droop of 36. 6mV for rising edge and−15.99 mV for falling edge over a 100μA to 75 mA step-change in10 ns has been observed.

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  • 134.
    Bao, Chunxiong
    et al.
    Linköping University, Department of Physics, Chemistry and Biology, Biomolecular and Organic Electronics. Linköping University, Faculty of Science & Engineering. Shenzhen Univ, Peoples R China.
    Xu, Weidong
    Linköping University, Department of Physics, Chemistry and Biology, Biomolecular and Organic Electronics. Linköping University, Faculty of Science & Engineering. Nanjing Tech Univ NanjingTech, Peoples R China.
    Yang, Jie
    Linköping University, Department of Physics, Chemistry and Biology, Biomolecular and Organic Electronics. Linköping University, Faculty of Science & Engineering. Shenzhen Univ, Peoples R China.
    Bai, Sai
    Linköping University, Department of Physics, Chemistry and Biology, Biomolecular and Organic Electronics. Linköping University, Faculty of Science & Engineering.
    Teng, Pengpeng
    Linköping University, Department of Physics, Chemistry and Biology, Biomolecular and Organic Electronics. Linköping University, Faculty of Science & Engineering. Nanjing Univ Aeronaut and Astronaut, Peoples R China.
    Yang, Ying
    Nanjing Univ Aeronaut and Astronaut, Peoples R China.
    Wang, Jianpu
    Nanjing Tech Univ NanjingTech, Peoples R China.
    Zhao, Ni
    Chinese Univ Hong Kong, Peoples R China.
    Zhang, Wenjing
    Shenzhen Univ, Peoples R China.
    Huang, Wei
    Nanjing Tech Univ NanjingTech, Peoples R China; NPU, Peoples R China.
    Gao, Feng
    Linköping University, Department of Physics, Chemistry and Biology, Biomolecular and Organic Electronics. Linköping University, Faculty of Science & Engineering.
    Bidirectional optical signal transmission between two identical devices using perovskite diodes2020In: NATURE ELECTRONICS, ISSN 2520-1131, Vol. 3, no 3, p. 156-164Article in journal (Refereed)
    Abstract [en]

    A solution-processed perovskite diode that functions as both optical transmitter and receiver can be used to build a monolithic pulse sensor and a bidirectional optical communication system. The integration of optical signal generation and reception into one device-thus allowing a bidirectional optical signal transmission between two identical devices-is of value in the development of miniaturized and integrated optoelectronic devices. However, conventional solution-processable semiconductors have intrinsic material and design limitations that prevent them from being used to create such devices with a high performance. Here we report an efficient solution-processed perovskite diode that is capable of working in both emission and detection modes. The device can be switched between modes by changing the bias direction, and it exhibits light emission with an external quantum efficiency of over 21% and a light detection limit on a subpicowatt scale. The operation speed for both functions can reach tens of megahertz. Benefiting from the small Stokes shift of perovskites, our diodes exhibit a high specific detectivity (more than 2 x 10(12) Jones) at its peak emission (~804 nm), which allows an optical signal exchange between two identical diodes. To illustrate the potential of the dual-functional diode, we show that it can be used to create a monolithic pulse sensor and a bidirectional optical communication system.

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  • 135.
    Bao, Chunxiong
    et al.
    Linköping University, Department of Physics, Chemistry and Biology, Biomolecular and Organic Electronics. Linköping University, Faculty of Science & Engineering. Shenzhen Univ, Peoples R China.
    Yang, Jie
    Linköping University, Department of Physics, Chemistry and Biology, Biomolecular and Organic Electronics. Linköping University, Faculty of Science & Engineering. Southeast Univ, Peoples R China.
    Bai, Sai
    Linköping University, Department of Physics, Chemistry and Biology, Biomolecular and Organic Electronics. Linköping University, Faculty of Science & Engineering.
    Xu, Weidong
    Linköping University, Department of Physics, Chemistry and Biology, Biomolecular and Organic Electronics. Linköping University, Faculty of Science & Engineering.
    Yan, Zhibo
    Linköping University, Department of Physics, Chemistry and Biology, Biomolecular and Organic Electronics. Linköping University, Faculty of Science & Engineering. Nanjing Univ, Peoples R China.
    Xu, Qingyu
    Southeast Univ, Peoples R China.
    Liu, Junming
    Nanjing Univ, Peoples R China.
    Zhang, Wenjing
    Shenzhen Univ, Peoples R China.
    Gao, Feng
    Linköping University, Department of Physics, Chemistry and Biology, Biomolecular and Organic Electronics. Linköping University, Faculty of Science & Engineering.
    High Performance and Stable All-Inorganic Metal Halide Perovskite-Based Photodetectors for Optical Communication Applications2018In: Advanced Materials, ISSN 0935-9648, E-ISSN 1521-4095, Vol. 30, no 38, article id 1803422Article in journal (Refereed)
    Abstract [en]

    Photodetectors are critical parts of an optical communication system for achieving efficient photoelectronic conversion of signals, and the response speed directly determines the bandwidth of the whole system. Metal halide perovskites, an emerging class of low-cost solution-processed semiconductors, exhibiting strong optical absorption, low trap states, and high carrier mobility, are widely investigated in photodetection applications. Herein, through optimizing the device engineering and film quality, high-performance photodetectors based on all-inorganic cesium lead halide perovskite (CsPbIxBr3-x), which simultaneously possess high sensitivity and fast response, are demonstrated. The optimized devices processed from CsPbIBr2 perovskite show a practically measured detectable limit of about 21.5 pW cm(-2) and a fast response time of 20 ns, which are both among the highest reported device performance of perovskite-based photodetectors. Moreover, the photodetectors exhibit outstanding long-term environmental stability, with negligible degradation of the photoresponse property after 2000 h under ambient conditions. In addition, the resulting perovskite photodetector is successfully integrated into an optical communication system and its applications as an optical signal receiver on transmitting text and audio signals is demonstrated. The results suggest that all-inorganic metal halide perovskite-based photodetectors have great application potential for optical communication.

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  • 136.
    Baral, Shawon Kumar
    Linköping University, Department of Electrical Engineering, Vehicular Systems.
    Closed Loop Control of PMSM Motor: Field Oriented Control Using Hall Sensors2021Independent thesis Advanced level (degree of Master (Two Years)), 20 credits / 30 HE creditsStudent thesis
    Abstract [en]

    Fossil-fuel vehicles are one of the main causes of CO2 emissions nowadays. As we are moving toward cleaner environment electrification of vehicles are becoming more and more popular. With the environment in mind, the recent improvement in battery technology and electronics has drawn a lot of attention to Brushless DC or BLDC  motors. Due to their high torque output and robust design, BLDC motors are a popular choice as the main propulsion unit in electric vehicles.  Permanent magnet synchronous motor, PMSM, is also a brushless dc motor with minor changes in design. So the word BLDC and PMSM is used interchangeably. In this thesis, two motor control algorithms were investigated. 6-Step control and Field oriented control or FOC. A three-phase inverter allows these motors to be driven by a battery. But when battery voltage goes down the speed of the motor also goes down. This thesis investigates a method to maintain the same speed at lower dc voltage. Also running of other motors than the control system was designed for. The control system performs well in simulation for two of the motor tested with the FOC algorithm. Simulation results show that the control system can track speed and current references with minimum error. Speed controller and current controllers control each parameter independently to control the motor. Low battery simulations provide useful data that shows how the field weakening technique makes it possible to achieve higher speed at low dc voltages.

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  • 137.
    Barsk, Niklas
    Linköping University, Department of Electrical Engineering.
    Ogg Vorbis decoder for Motorola DSP560022004Independent thesis Basic level (professional degree)Student thesis
    Abstract [en]

    Ogg Vorbis is a rather new audio format with some similarities with other more known formats such as MP3 and WMA. It is generally accepted to have a better audio quality than most competing formats and it is in contrast to many of its competitors totally licence and royalty free.

    The goal with this thesis is to port the existing fixed point decoder Tremor, which is written in C, to Motorola's DSP56002. The DSP has a very limited amount of memory so some optimizations has to be made to be able to run Tremor successfully.

    The report presents the necessary steps taken to port Tremor to the DSP and the difficulties of this process. It also describes the memory and CPU usage of the DSP when running Tremor and other results of the port.

    A description as well as examples and workarounds of bugs found in the compiler g56k is attached to this report.

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  • 138.
    Bashir, Fayyaz
    Linköping University, Department of Science and Technology, Physics and Electronics. Linköping University, The Institute of Technology.
    Design and Characterization of Dual Polarized feed for Satellite Communication Antenna2012Independent thesis Advanced level (degree of Master (Two Years)), 20 credits / 30 HE creditsStudent thesis
    Abstract [en]

    So far, extensive research has been made, and researchers have shown that use of septum polarizer for feed designing not only provides the dual polarization but also improve the input reflection and cross-polar isolation performance of the feed.

    In this thesis design of the feed for satellite communication antenna has been investigated, which provides the transmission in right hand circular polarization and reception in left hand circular polarization. A feed which covers both receives and transmits bands, i.e. (7.25-7.75 GHz) and (7.9-8.4 GHz) was designed by using the low axial ratio stepped septum polarizer in square waveguide technology, and the circular horn with the round ring choke at the aperture of the feed. Choke at the aperture of the feed was reduced the level of side and back lobes and improves the gain and efficiency of the reflector antenna by putting more energy at the aperture of the reflector antenna. The excitation of the feed has been done by using the standard WR-112 rectangular waveguide at the input of the feed.

    Design and optimization of the feed have been done in High frequency structure simulator (HFSS) tool, and the simulation results show the input reflection performance of the feed less than -18 dB and the cross-polar isolation better than 25 dB. Finally, the optimized design of feed has been fabricated and measured results show that feed has reasonable input reflection and good cross-polar isolation performance over the entire bandwidth.

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  • 139.
    Behnam, Henry
    Linköping University, Department of Science and Technology.
    Konstruktion och byggnation av testfixtur för 10Gbit/s transpondermoduler2002Independent thesis Basic level (professional degree)Student thesis
    Abstract [en]

    This thesis for the Master of Science degree was performed at Solectron Corporation in Norrköping. The background for the thesis was a need to develop and build two test fixtures to automatize testing and adjusting of transmitter modules (TX-fixture) and receiver modules (RX-fixture) which are head devices in DWDM-systems. The basic elements for the test fixtures are: Test board, switch board and DC/DC board.

    The main function of the test board is to handle communication between the transmitter and receiver modules and supply voltage to these modules. The test board was insufficient and modified with a microprocessor to handle the communication between the PC and the receiver module. There are two connectors (NexLev) on test board to connect the receiver and transmitter modules.

    The switchboard has been used in fixtures for testing and adjusting both the receiver and transmitter modules for data rate up to 2.5 Gbit/s. This board has been modified for use in new fixtures for data rate up to 10Gbit/s.

    Because the power consumption of the test module will be measured with the amperemeter in the power supply, the reference module and the test module cannot be supplied by the same power supply. Because of high cost and the fact that no current is measured it is unacceptable to use a power supply to feed the reference module. The solution is to build a DC/DC board.

    Because the NexLev connector has a durability of 30-40 times it was necessary to have a connector with higher durability. This connector is located between the test board and the test module. Without this connector the project will not be profitable for the company.

    Some parts in RX- and TX-fixture have been used in older versions of fixtures for data rate up to 2.5Gbit/s. These parts have been updated for the new test demands of the new fixtures.

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  • 140.
    Bendtsen, Marcus
    Linköping University, Department of Computer and Information Science. Linköping University, The Institute of Technology.
    Development and piloting of a fully automated, push based, extended session alcohol intervention on university students: a feasibility study2013Independent thesis Advanced level (degree of Master (One Year)), 20 credits / 30 HE creditsStudent thesis
    Abstract [en]

    Alcohol consumption amongst university students in Sweden has repeatedly been measured to be at risky levels for more than 50% of students. Internet based brief interventions aimed to intervene and prevent risky drinking have been developed with some success during recent years. Single session interventions have been implemented into routine practice in Sweden and other countries, however not all risky drinkers benefit from these single session brief interventions.

    This feasibility study attempted to develop and pilot an extended session intervention, where participants received messages with motivating content several times a week for a few weeks. All students on semester 1, 3 and 5 at Linköpings Universisty were invited to join a brief single session intervention as part of routine practice, and those who completed the single session intervention were invited to join the new extended intervention.

    Out of a total of 11,284 students that were invited to complete the single session intervention 4916 (%=43.6) responded. Out of these 1216 (%=24.7) decided to enrol to the extended intervention and 898 (%=77.9) completed the follow up questionnaire after the extended intervention. Participants that enrolled to the extended intervention were automatically placed in a draw for one of two iPads.

    Issues were found with participants that wanted to receive messages via SMS, as 28.3% didn’t activate their SMS intervention and hence didn’t enrol to the extended intervention. Furthermore there was some indication that participants exposed to more messages were more positive towards the content, as were participants receiving SMS messages over email message. This might be an indication that email may not be up to par with SMS for delivering this type of intervention.

    The study showed that this kind of extended intervention is worthwhile pursuing. Risky drinkers were more likely to find the intervention useful, and a majority of all participants would possibly or definitely recommend the intervention to a friend that needed help with their alcohol consumption. Future studies should focus on decreasing the number of participants not activating their SMS intervention, experimenting with enrolment without any prize and possibly detached from single session intervention, measuring the effect on alcohol consumption of the intervention as well as identifying any differences between receiving the intervention via email or SMS.

    The responsibility of expanding and enhancing the research of fully automated brief interventions lay upon researches from several fields. There is a need of refining the human--‐computer interaction as well as the content and design of the intervention. This cannot occur effectively from a single department but should be a joint venture in order to be cost effective and to utilize expertise.

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  • 141.
    Bendz Sörensson, Emil
    et al.
    Linköping University, Department of Science and Technology, Physics, Electronics and Mathematics. Linköping University, Faculty of Science & Engineering.
    Carlsson, John
    Linköping University, Department of Science and Technology, Physics, Electronics and Mathematics. Linköping University, Faculty of Science & Engineering.
    Development of PCB-integrated mmWave antenna2022Independent thesis Advanced level (degree of Master (Two Years)), 20 credits / 30 HE creditsStudent thesis
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  • 142.
    Bengtsson, Carl Johan
    Linköping University, Department of Electrical Engineering.
    SmartMedia-controller på chip2002Independent thesis Basic level (professional degree)Student thesis
    Abstract [en]

    This report deals with the design of a controller for SmartMedia™ flash memory cards, based on a hardware description found in the SmartMedia™ Interface Library - SMIL.

    The design was made on logic gate level, using standard cells in OrCAD Capture. After simulation of the design in PSpice A/D, it was exported as an EDIF netlist, which was used to make a chip layout in L-Edit, a layout tool for making integrated circuits. The layout was made using a method called Standard Place and Route - SPR, where the layout tool places standard cells from a library and connects them according to the EDIF netlist.

    A netlist which could be simulated in PSpice was extracted from the finished chip layout to verify that the function of the design was the same as before the transition from schematic to layout.

    The standard cells in the library used to make the chip layout have to meet certain criteria in order for both SPR and extraction to work and this is also discussed.

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  • 143.
    Bengtsson, Filip
    et al.
    Linköping University, Department of Science and Technology, Physics and Electronics. Linköping University, Faculty of Science & Engineering.
    Sköld, David
    Linköping University, Department of Science and Technology, Physics and Electronics. Linköping University, Faculty of Science & Engineering.
    Analysis of angular accuracy in the IFF Monopulse receiver2018Independent thesis Advanced level (degree of Master (Two Years)), 20 credits / 30 HE creditsStudent thesis
    Abstract [en]

    This master thesis investigates how certain components error margin may affect the accuracy of a IFF monopulse receiver. The IFF monopulse receiver measures the angle of arrival of the incident signal by comparing sum and difference signals created in the receiver. The components of interest are phase shifters and attenuators, where both can give individual and different errors depending on the antenna steering angle. The project is conducted at Saab Aeronautics, based on a receiver in development for the Gripen E aircraft. The results of the thesis generated results showing that the angular accuracy decreases with the increase of steering angle. The angular deviation can for some cases be seen as sufficiently small for the receiver to work properly in the ideal case.

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    Analysis of angular accuracy in the IFF Monopulse receiver
  • 144.
    Bengtsson, Fredrik
    et al.
    Linköping University, Department of Electrical Engineering.
    Berglund, Rikard
    Linköping University, Department of Electrical Engineering.
    Digital compensation of distortion in audio systems2010Independent thesis Advanced level (professional degree), 20 credits / 30 HE creditsStudent thesis
    Abstract [en]

    The advancements of computational power in low cost FPGAs are giving the opportunityto implement real-time compensation of loudspeakers and audio systems. The need for expensive commercial audio systems is reduced when the fidelity ofmuch cheaper audio systems easily can be improved by real-time compensation. The topic of this thesis is to investigate and evaluate methods for digital compensationof distortion in audio systems. More specifically, a VHDL module isimplemented to, when necessary, alleviate the problem of drastically deterioratingfidelity of the bass appearing when the input power is too high.

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  • 145.
    Bengtsson, Johnny
    Linköping University, Department of Science and Technology.
    Forensisk hårddiskkloning och undersökning av hårddiskskrivskydd2004Independent thesis Basic level (professional degree)Student thesis
    Abstract [sv]

    Detta examensarbete reder ut arbetsprinciperna för olika typer av hårddiskskrivskydd; hårdvaruskrivskydd, mjukvaruskrivskydd, hybridskrivskydd och bygelskrivskydd. Slutsatsen av utredningen är att endast hårdvaruskrivskydd Detta examensarbete reder ut arbetsprinciperna för olika typer av hårddiskskrivskydd; hårdvaruskrivskydd, mjukvaruskrivskydd, hybridskrivskydd och bygelskrivskydd. Slutsatsen av utredningen är att endast hårdvaruskrivskydd bedöms ha tillräckligt pålitliga skyddsprinciper, vilket motiveras av dess oberoende från både hårdvara och operativsystem.

    Vidare undersöks hårdvaruskrivskyddet Image MASSter(TM) Drive Lock från Intelligent Computer Solutions (ICS). Några egentliga slutsatser gick inte dra av kretskonstruktionen, bortsett från att den är uppbyggd kring en FPGA (Xilinx Spartan-II, XC2S15) med tillhörande PROM (XC17S15APC).

    En egenutvecklad idé till autenticieringsmetod för hårddiskkloner föreslås som ett tillägg till arbetet. Principen bygger på att komplettera hårddiskklonen med unik information om hårddisk såväl kloningsomständigheter, vilka sammanflätas genom XOR-operation av komponenternas hashsummor.Autenticieringsmetoden kan vid sjösättning möjligen öka rättsäkerheten för både utredarna och den som står misstänkt vid en brottsutredning.

    Arbetet är till stora delar utfört vid och på uppdrag av Statens kriminaltekniska laboratorium (SKL) i Linköping.

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  • 146.
    Bengtsson, Richard
    et al.
    Linköping University, Department of Electrical Engineering, Integrated Circuits and Systems.
    Lindgren, Joel
    Linköping University, Department of Electrical Engineering, Integrated Circuits and Systems.
    Portabel EKG: Med möjlighet att trådlöst överföra och behandla EKG-data2020Independent thesis Basic level (degree of Bachelor), 10,5 credits / 16 HE creditsStudent thesis
    Abstract [en]

    Cardiovascular disease is the most common cause of death in Sweden and if these heart defects can be diagnosed at an early stage, the chance of survival in the sufferer is very high. This project involved designing a modular and portable ECG system that can measure at least seven leads and wirelessly over Bluetooth Low Energy transfer ECG data to a computer or mobile where it can be saved for later analysis. The three modules used in the project are a demonstration board from Texas Instrument, which builds around the analog to digital converter ADS1298 designed to collect ECG data, Nordic Thingy 52 which wirelessly via Bluetooth Low Energy transmits the collected ECG data and a Raspberry Pi for storage and data management. The measured values ​​must be saved in a file that can later be used to visualize an ECG complex. 

    The work began with a feasibility study and a design specification as a basis for the ECG system. When the system was implemented several different ECGs was done to test so that data transfer and filtering were correct. The completed ECG system proved to meet the requirements set at the beginning of the project and has a very high potential for improvement in the future. 

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  • 147.
    Benselfelt, Tobias
    et al.
    KTH Royal Inst Technol, Sweden.
    Shakya, Jyoti
    KTH Royal Inst Technol, Sweden.
    Rothemund, Philipp
    Max Planck Inst Intelligent Syst, Germany.
    Lindström, Stefan
    Linköping University, Department of Management and Engineering, Solid Mechanics. Linköping University, Faculty of Science & Engineering.
    Piper, Andrew
    KTH Royal Inst Technol, Sweden.
    Winkler, Thomas E.
    Tech Univ Carolo Wilhelmina Braunschweig, Germany; Tech Univ Carolo Wilhelmina Braunschweig, Germany.
    Hajian, Alireza
    KTH Royal Inst Technol, Sweden.
    Wagberg, Lars
    KTH Royal Inst Technol, Sweden.
    Keplinger, Christoph
    Max Planck Inst Intelligent Syst, Germany; Univ Colorado, CO 80309 USA; Univ Colorado, CO 80309 USA.
    Hamedi, Mahiar Max
    KTH Royal Inst Technol, Sweden.
    Electrochemically Controlled Hydrogels with Electrotunable Permeability and Uniaxial Actuation2023In: Advanced Materials, ISSN 0935-9648, E-ISSN 1521-4095, Vol. 35, no 45, article id 2303255Article in journal (Refereed)
    Abstract [en]

    The unique properties of hydrogels enable the design of life-like soft intelligent systems. However, stimuli-responsive hydrogels still suffer from limited actuation control. Direct electronic control of electronically conductive hydrogels can solve this challenge and allow direct integration with modern electronic systems. An electrochemically controlled nanowire composite hydrogel with high in-plane conductivity that stimulates a uniaxial electrochemical osmotic expansion is demonstrated. This materials system allows precisely controlled shape-morphing at only -1 V, where capacitive charging of the hydrogel bulk leads to a large uniaxial expansion of up to 300%, caused by the ingress of & AP;700 water molecules per electron-ion pair. The material retains its state when turned off, which is ideal for electrotunable membranes as the inherent coupling between the expansion and mesoporosity enables electronic control of permeability for adaptive separation, fractionation, and distribution. Used as electrochemical osmotic hydrogel actuators, they achieve an electroactive pressure of up to 0.7 MPa (1.4 MPa vs dry) and a work density of & AP;150 kJ m-3 (2 MJ m-3 vs dry). This new materials system paves the way to integrate actuation, sensing, and controlled permeation into advanced soft intelligent systems. The unique properties of hydrogels enable the design of life-like soft intelligent systems. This work demonstrates how the swelling of hydrogels from cellulose nanofibrils and carbon nanotubes can be electrochemically controlled to achieve electrochemical osmotic actuation. This new materials system paves the way for integrated actuation, sensing, and controlled permeation in electrotunable separation membranes or soft actuators.image

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  • 148.
    Berg, Amanda
    Linköping University, Department of Electrical Engineering, Computer Vision. Linköping University, The Institute of Technology.
    Classification of leakage detections acquired by airborne thermography of district heating networks2013Independent thesis Advanced level (degree of Master (Two Years)), 20 credits / 30 HE creditsStudent thesis
    Abstract [en]

    In Sweden and many other northern countries, it is common for heat to be distributed to homes and industries through district heating networks. Such networks consist of pipes buried underground carrying hot water or steam with temperatures in the range of 90-150 C. Due to bad insulation or cracks, heat or water leakages might appear.

    A system for large-scale monitoring of district heating networks through remote thermography has been developed and is in use at the company Termisk Systemteknik AB. Infrared images are captured from an aircraft and analysed, finding and indicating the areas for which the ground temperature is higher than normal. During the analysis there are, however, many other warm areas than true water or energy leakages that are marked as detections. Objects or phenomena that can cause false alarms are those who, for some reason, are warmer than their surroundings, for example, chimneys, cars and heat leakages from buildings.

    During the last couple of years, the system has been used in a number of cities. Therefore, there exists a fair amount of examples of different types of detections. The purpose of the present master’s thesis is to evaluate the reduction of false alarms of the existing analysis that can be achieved with the use of a learning system, i.e. a system which can learn how to recognize different types of detections. 

    A labelled data set for training and testing was acquired by contact with customers. Furthermore, a number of features describing the intensity difference within the detection, its shape and propagation as well as proximity information were found, implemented and evaluated. Finally, four different classifiers and other methods for classification were evaluated.

    The method that obtained the best results consists of two steps. In the initial step, all detections which lie on top of a building are removed from the data set of labelled detections. The second step consists of classification using a Random forest classifier. Using this two-step method, the number of false alarms is reduced by 43% while the percentage of water and energy detections correctly classified is 99%.

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  • 149.
    Bergfalck, Ludwig
    et al.
    Linköping University, Department of Science and Technology. Linköping University, Faculty of Science & Engineering.
    Engström, Johannes
    Linköping University, Department of Science and Technology. Linköping University, Faculty of Science & Engineering.
    Designing a Physical Unclonable Function for Cryptographic Hardware2021Independent thesis Advanced level (degree of Master (Two Years)), 20 credits / 30 HE creditsStudent thesis
    Abstract [en]

    Hardware Security Modules (HSMs) are embedded systems that provide a physically secure data storage and handling environment. This master thesis evaluates an HSM method incorporating cryptographic key generation, key management, and tamper protection. The HSM concept involves a sensing mesh structured Physical Unclonable Function (PUF), where the cryptographic key is derived from the sum of cross-sectional area capacitance between conductors on adjacent layers of a flex PCB forming a grid. This sensing mesh PUF that stores a digital fingerprint in its microstructure is used to enclose an internal system extracting and managing the keys. This ensures that accessing the internal structure is unmanageable without modifying the enclosure. Since the cryptographic key is derived from the intrinsic properties within the sensing mesh, modifying it will change its intrinsic properties and change the cryptographic key and make it unusable. The Master thesis contains PCB design and development of a prototype of the PUF system and an associated capacitance measurement system, which can handle and extract unique keys from each copy of the PUFs. A hardware assembling, experimenting, and evaluation procedure were performed regarding the robustness of the PUF and its susceptibility to environmental impacts such as temperature changes, invasive attacks, and agitation. Additionally, an performance evaluation is made by estimating a set of quality factors often associated with PUFs, such as uniqueness, reliability, uniformity, and bit-aliasing on the extracted cryptographic keys. The cryptographic keys provide good reliability in stable conditions for each PUF copy of the population. The cryptographic keys also provide gooduniqueness, uniformity, and bit-aliasing estimations with the quality factors. Moreover, an invasive attack experiment indicates that the PUF enclosure prototype provides tamper detection possibilities together with distinct structure modifications when an intrusion attempt is performed. As stated in theory, PUFs are sensitive to environmental changes, which is also observable in the results when the PUF enclosure prototype is exposed to various environmental conditions.

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  • 150.
    Berggren, Henrik
    et al.
    Linköping University, Department of Electrical Engineering, Vehicular Systems.
    Melin, Martin
    Linköping University, Department of Electrical Engineering, Vehicular Systems.
    UKF and EKF with time dependent measurement and model uncertainties for state estimation in heavy duty diesel engines2011Independent thesis Advanced level (degree of Master (Two Years)), 20 credits / 30 HE creditsStudent thesis
    Abstract [en]

    The continuous challenge to decrease emissions, sensor costs and fuel consumption in diesel engines is battled in this thesis. To reach higher goals in engine efficiency and environmental sustainability the prediction of engine states is essential due to their importance in engine control and diagnosis. Model output will be improved with help from sensors, advanced mathematics and non linear Kalman filtering. The task consist of constructing non linear Kalman Filters and to adaptively weight measurements against model output to increase estimation accuracy. This thesis shows an approach of how to improve estimates by nonlinear Kalman filtering and how to achieve additional information that can be used to acquire better accuracy when a sensor fails or to replace existing sensors. The best performing Kalman filter shows a decrease of the Root Mean Square Error of 75 % in comparison to model output.

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