liu.seSearch for publications in DiVA
Change search
Refine search result
1234567 51 - 100 of 1212
CiteExportLink to result list
Permanent link
Cite
Citation style
  • apa
  • ieee
  • modern-language-association-8th-edition
  • vancouver
  • oxford
  • Other style
More styles
Language
  • de-DE
  • en-GB
  • en-US
  • fi-FI
  • nn-NO
  • nn-NB
  • sv-SE
  • Other locale
More languages
Output format
  • html
  • text
  • asciidoc
  • rtf
Rows per page
  • 5
  • 10
  • 20
  • 50
  • 100
  • 250
Sort
  • Standard (Relevance)
  • Author A-Ö
  • Author Ö-A
  • Title A-Ö
  • Title Ö-A
  • Publication type A-Ö
  • Publication type Ö-A
  • Issued (Oldest first)
  • Issued (Newest first)
  • Created (Oldest first)
  • Created (Newest first)
  • Last updated (Oldest first)
  • Last updated (Newest first)
  • Disputation date (earliest first)
  • Disputation date (latest first)
  • Standard (Relevance)
  • Author A-Ö
  • Author Ö-A
  • Title A-Ö
  • Title Ö-A
  • Publication type A-Ö
  • Publication type Ö-A
  • Issued (Oldest first)
  • Issued (Newest first)
  • Created (Oldest first)
  • Created (Newest first)
  • Last updated (Oldest first)
  • Last updated (Newest first)
  • Disputation date (earliest first)
  • Disputation date (latest first)
Select
The maximal number of hits you can export is 250. When you want to export more records please use the Create feeds function.
  • 51.
    Andersson, Niklas
    et al.
    Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology. Telefonaktiebolaget L M Ericsson, Stockholm.
    Vesterbacka, Mark
    Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
    Wikner, Jacob
    Linköping University, Department of Electrical Engineering, Electronics System. Telefonaktiebolaget L M Ericsson, Stockholm.
    Rudberg, Mikael
    Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology. Telefonaktiebolaget L M Ericsson, Stockholm.
    Förfarande för scrambling av dataord och scrambler2000Patent (Other (popular science, discussion, etc.))
  • 52.
    Andersson, Niklas
    et al.
    Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
    Wikner, Jacob
    Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
    A strategy for implementing dynamic element matching in current-steering DACs2000In: Mixed-Signal Design, 2000. SSMSD. 2000 Southwest Symposium on, IEEE , 2000, p. 51-56Conference paper (Other academic)
    Abstract [en]

    Interesting comparisons of dynamic element matching (DEM) techniques, have been presented during the last decade. However, not many chip implementations of these DEM techniques have been presented so far. A brief review of different DEM techniques are presented in this paper together with a strategy for implementing the partial randomization DEM, PRDEM, technique in a 3.3 V supply, 14 bit CMOS current-steering wideband digital-to-analog converter (DAC)

  • 53.
    Andersson, Niklas
    et al.
    Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
    Wikner, Jacob
    Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
    Comparison of Different Dynamic Element Matching Techniques for Wideband CMOS DACs1999In: Proceedings of the 17th Norchip Conference, 1999Conference paper (Other academic)
    Abstract [en]

    In the field of dynamic element matching, DEM, techniques, some ”new” important theoretical results have been presented during the last decade. However, no comparison between these different DEM techniques (FRDEM, PRDEM, NSDEM) used in wideband digital-to-analog converters, DACs, has been reported. A brief review of different DEM techniques and a comparison between their properties in terms of complexity, etc., are presented in this paper together with simulation results showing the impact of using different DEM techniques.

  • 54.
    Andersson, Ola
    Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
    Modeling and Implementation of Current-Steering Digital-to-Analog Converters2005Doctoral thesis, monograph (Other academic)
    Abstract [en]

    Data converters, i.e., analog-to-digital converters (ADCs) and digital-to-analog converters (DACs), are interface circuits between the analog and digital domains. They are used in, e.g., digital audio applications, data communication applications, and other types of applications where conversion between analog and digital signal representation is required. This work covers different aspects related to modeling, error correction, and implementation of DACs for communication applications where the requirements on the circuits in terms of speed and linearity are hard. The DAC architecture considered in this work is the current-steering DAC, which is the most commonly used architecture for high-speed applications.

    Transistor-level simulation of complex circuits using accurate transistor models require long simulation times. A transistor-level model of a DAC used in a system simulation is likely to be a severe bottleneck limiting the overall system simulation speed. Moreover, investigations of stochastic parameter variations require multiple simulation runs with different parameter values making transistor-level models unsuitable. Therefore, there is a need for behavioral-level models with reasonably short simulation times. Behavioral-level models can also be used to find the requirements on different building blocks on high abstraction levels, enabling the use of efficient topdown design methodologies. Models of different nonideal properties in current-steering DACs are used and developed in this work.

    Static errors typically dominates the low-frequency behavior of the DAC. One of the limiting factors for the static linearity of a current-steering DAC is mismatch between current sources. A well-known model of this problem is used extensively in this work for evaluation of different ideas and techniques for linearity enhancement. The highfrequency behavior of the DAC is typically dominated by dynamic errors. Models oftwo types of dynamic errors are developed in this work. These are the dynamic errors caused by parasitic capacitance in wires and transistors and glitches caused by asymmetry in the settling behavior of a current source.

    The encoding used for the digital control word in a current steering DAC has a large influence on the circuit performance, e.g., in terms static linearity and glitches. In this work, two DAC architectures are developed. These are denoted the decomposed and partially decomposed architectures and utilize encoding strategies aiming at a high circuit performance by avoiding unnecessary switching of current sources. The developed architectures are compared with the well-known binary-weighted and segmented architectures using behavioral-level simulations.

    It can be hard to meet a DAC design specification using a straightforward implementation. Techniques for compensation of errors that can be applied to improve the DAC linearity are studied. The well-known dynamic element matching (DEM) techniques are used for transforming spurious tones caused by matching errors into white or shaped noise. An overview of these techniques are given in this work and a DEM technique for the decomposed DAC architecture is developed. In DS modulation, feedback of the quantization error is utilized to spectrally shape the quantization noise to reduce its power within the signal band. A technique based on this principle is developed for spectral shaping of DAC nonlinearity errors utilizing a DAC model in a feedback loop. Two examples of utilization of the technique are given.

    Four different current-steering DACs implemented in CMOS technology are developed to enable comparison between behavioral-level simulations and measurements on actual implementations and to provide platforms for evaluation of different techniques for linearity improvement. For example, a 14-bit DEM DAC is implemented and measurement results are compared with simulation results. A good agreement between measured and simulated results is obtained. Moreover, a configurable 12-bit DAC capable of operating with different degrees of segmentation and decomposition is implemented to evaluate the proposed decomposed architecture. Measurement results agree with results from behavioral-level simulations and indicate that the decomposed architecture is a viable alternative to the commonly used segmented architecture.

    Download full text (pdf)
    FULLTEXT01
  • 55.
    Andersson, Ola
    et al.
    Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
    Andersson, Niklas
    n/a.
    Vesterbacka, Mark
    Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
    Wikner, Jacob
    Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
    A 14-Bit dual current-steering DAC2003In: Proc. Swedish System-on-Chip Conf., SSoCC'03, 2003Conference paper (Other academic)
    Abstract [en]

    A 14-bit dual current-steering digital-to-analog converter implemented in a 0.25 µm CMOS process is presented in this work. Both implementation issues and measurement results are presented. The measured spurious-free dynamic range is higher than 73 dB for signal frequencies up to 3 MHz, and a measured multi-tone power ratio of approximately 71 dB is reported for an ADSL-like input.

  • 56.
    Andersson, Ola
    et al.
    Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
    Andersson, Niklas
    n/a.
    Vesterbacka, Mark
    Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
    Wikner, Jacob
    Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
    A differential DAC architecture with variable common-mode level2002In: Proc. 2002 IEEE Int. Symp. on Circuits and Systems, ISCAS'02, 2002, p. I-113-I-116Conference paper (Refereed)
    Abstract [en]

    A differential current-steering digital-to-analog converter (DAC) architecture allowing the common-mode level of the input signal to be varied is presented. Simulation results with models of different DAC nonlinearities indicate that the proposed architecture has a potential of improving the linearity of the converters.

  • 57.
    Andersson, Ola
    et al.
    Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
    Andersson, Niklas
    n/a.
    Vesterbacka, Mark
    Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
    Wikner, Jacob
    Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
    A method of segmenting digital-to-analog converters2003In: Proc. IEEE Southwest Symposium on Mixed-Signal Design, SSMSD'03, 2003, p. 32-37Conference paper (Refereed)
    Abstract [en]

    Segmented architectures are often used in digital-to-analog converters (DACs). Here we propose a DAC structure based on recursive decomposition of an N-bit binary DAC into two (N-1) bit DACs and one 1 bit DAC. A DAC model that includes matching errors has been simulated. The simulation results indicate that by using four layers of decomposition it is possible to achieve similar performance as when using seven bits of traditional segmentation.

  • 58.
    Andersson, Ola
    et al.
    Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
    Andersson, Niklas
    n/a.
    Vesterbacka, Mark
    Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
    Wikner, Jacob
    Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
    Combining DACs for improved performance2002In: Proc. 4th IEE Int. Conf. on Advanced A/D and D/A Conversion Techniques and their Applications, ADDA'02, 2002Conference paper (Refereed)
    Abstract [en]

    This work is an overview of recently proposed methods on combining DACs in order to improve performance. Some further development of these techniques are also presented. The techniques aim at reducing glitches and sensitivity towards limited output impedance in current sources.

  • 59.
    Andersson, Ola
    et al.
    Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
    Andersson, Niklas
    Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
    Wikner, Jacob
    Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
    Spectral shaping of DAC nonlinearity errors through modulation of expected errors2001In: Circuits and Systems, 2001. ISCAS 2001. The 2001 IEEE International Symposium on, IEEE , 2001, Vol. 3, p. 417-420Conference paper (Refereed)
    Abstract [en]

    Traditionally, delta-sigma modulation has been used for shaping of quantization noise. We present a modified version of delta-sigma modulation which also takes into account unwanted nonlinearities by feeding back not only the quantization error, but also the expected physical error. Behavioral-level simulations of a 5th-order structure showing an improvement of up to 4 effective bits are included

  • 60.
    Andersson, Ola
    et al.
    Linköping University, Department of Electrical Engineering.
    Vesterbacka, Mark
    Linköping University, Department of Electrical Engineering. Linköping University, Department of Electrical Engineering, Electronics System.
    A parameterized cell-based design approach for digital-to-analog converters2004In: Proc. IEEE Int. Workshop on System-on-Chip for Real-Time Applications, IWSOC'04, 2004, p. 225-228Conference paper (Refereed)
    Abstract [en]

    Due to the lack of proper design automation tools, designers are often forced to use full-custom design methodologies when designing analog and mixed-signal circuits. In this work, we discuss a design methodology based on parameterized cells intended for efficient design. The methodology is illustrated with the design of a 12-bit configurable current-steering DAC. Because the cells are parameterized, their layout must be described in a generalized way, resulting in a longer design time compared with a manual layout of a fixed circuit. However, the parameterized approach simplifies iteration of the layout process and block reuse.

  • 61.
    Andersson, Ola
    et al.
    Linköping University, Department of Electrical Engineering.
    Vesterbacka, Mark
    Linköping University, Department of Electrical Engineering.
    A testbed for different codes in digital-to-analog converters2004In: Proc. Swedish System-on-Chip Conf. 2004, SSoCC'04, 2004Conference paper (Other academic)
  • 62.
    Andersson, Ola
    et al.
    Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Electronics System.
    Vesterbacka, Mark
    Linköping University, The Institute of Technology. Linköping University, Department of Electrical Engineering, Electronics System.
    A yield-enhancement strategy for binary-weighted DACs2005In: Proc. European Conf. Circuit Theory and Design 2005, ECCTD'05, 2005, , p. 55-58p. 55-58Conference paper (Refereed)
    Abstract [en]

    One of the major contributors to the static nonlinearity of a current-steering digital-to-analog converter (DAC) is mismatch between current sources. A technique for enhancing the yield of binary-weighted current-steering DACs is proposed. The technique utilizes a special case of a general technique for spectral shaping of DAC nonlinearity errors presented earlier and requires oversampling. The technique relies on two DAC models with low computational complexity that can be integrated with the DAC at a negligible cost in terms of area and power consumption. Behavioral-level simulation results indicate that the proposed method has a good potential of enhancing the yield of binary-weighted DACs for situations where the matching errors constitute the dominating source of nonlinearity.

  • 63.
    Andersson, Ola
    et al.
    Linköping University, Department of Electrical Engineering.
    Vesterbacka, Mark
    Linköping University, Department of Electrical Engineering. Linköping University, Department of Electrical Engineering, Electronics System.
    Dynamic element matching in decomposed digital-to-analog converters2004In: Proc. IEEE NORCHIP'04, Denmark: TechnoData A/S , 2004, , p. 187-190p. 187-190Conference paper (Refereed)
    Abstract [en]

    A dynamic element matching (DEM) technique is proposed that aims at improving the spurious-free dynamic range (SFDR) of current-steering digital-to-analog converters (DACs) implemented with a decomposed architecture. The architecture consists of a number of small binary-weighted DACs that are controlled such that only a minimum number of unit current sources are switching for the most critical code transitions. The DEM is obtained by scrambling bit pairs with equal weight. In contrast to most other DEM techniques, the scrambling is performed conditionally so that the number of switching current sources does not increase compared with the unscrambled case. Hence, the good glitch properties of the decomposed converter architecture are maintained. Simulations on a behavioral level of some decomposed DACs have been performed. Assuming random uncorrelated matching errors with Gaussian distribution and a 5% standard deviation, the SFDR value giving 90% yield is increased with 5.6 dB for a 14-bit DAC using scrambling of the two bit pairs with the largest weights. The hardware cost for the required scrambling circuits should be low since only two pairs of bits are scrambled.

  • 64. Andersson, Ola
    et al.
    Vesterbacka, Mark
    Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
    Modeling of glitches due to rise/fall asymmetry in current-steering digital-to-analog converters2005In: IEEE Transactions on Circuits and Systems I: Regular Papers, ISSN 1549-8328, Vol. 52, no 11, p. 2265-2275Article in journal (Refereed)
    Abstract [en]

    The current-steering digital-to-analog converter (DAC) is the most common type of DAC for high-speed applications. Glitches present in the DAC output contribute to nonlinear distortion in the DAC transfer characteristics degrading the circuit performance. One source of glitches is asymmetry in the settling behavior when switching on and off a current source. A behavioral-level model of this nonideal behavior is derived in this work. Further, a method with low computational complexity for estimating the influence of the modeled errors in the frequency domain is developed. This method can be utilized by circuit designers to derive circuit requirements for fulfilling a given frequency-domain specification, potentially relaxing the requirements compared with a worst-case analysis. Examples of model utilization are given in terms of an analytical examination and MATLAB simulations. A good agreement between simulated and analytical results is obtained.

  • 65.
    Andersson, Ola
    et al.
    Linköping University, Department of Electrical Engineering.
    Vesterbacka, Mark
    Linköping University, Department of Electrical Engineering. Linköping University, Department of Electrical Engineering, Electronics System.
    Partial decomposition of digital-to-analog converters2004In: Proc. 12th IEEE Mediterranean Electrotechnical Conf., MELECON'04, 2004, p. 193-196Conference paper (Refereed)
    Abstract [en]

    The decomposed DAC architecture was recently proposed as an alternative to the traditional segmented architecture. In this work, we present a modified version of the decomposed architecture with reduced hardware complexity denoted the partially decomposed architecture. Behavioral-level simulations indicate that the partially decomposed architecture is a good alternative for signals with Gaussian distribution, whereas the original decomposed or segmented architectures are preferred for sinusoidal signals.

  • 66.
    Andersson, Ola
    et al.
    Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
    Wikner, Jacob
    Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
    Characterization of a CMOS current-steering DAC using state-space models2000In: Circuits and Systems, 2000. Proceedings of the 43rd IEEE Midwest Symposium on, IEEE , 2000, Vol. 2, p. 668-671 vol.2Conference paper (Refereed)
    Abstract [en]

    Performance limitations on current-steering digital-to-analog converters (DACs) are due to finite output impedances, nonideal switches, parasitic capacitances, matching, etc. In this work we present a dynamic state-space model of a 14-bit current-steering DAC which includes dynamic nonidealities. Simulation results are presented and compared to measurement results. The model can be used for fast performance estimation of D/A converters

  • 67.
    Andersson, Ola
    et al.
    Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
    Wikner, Jacob
    Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
    Digital-to-analog converter having error correction2002Patent (Other (popular science, discussion, etc.))
    Abstract [en]

    The values X(n) input to a current-steering digital-to-analog converter (49) are modified (41) before the actual conversion to compensate for conversion errors of the digital-to-analog converter. The input values are modified according to a model (43) of the digital-to-analog converter in which each output value of the digital-to-analog converter Y(n) is a sum of a desired value directly proportional to the respective input value and an error. The error is a product of the settled output value, i.e. the difference between the desired value and the previous output value Y(n−1) actually provided by the digital-to-analog converter, and a relative step error that is a function only of the respective input signal and is stored in a table. The relative step error can be a function also of the previous output signal and of the previous input signal. This model has a low complexity and is suitable for on-chip implementation.

  • 68.
    Andersson, Ola
    et al.
    Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
    Wikner, Jacob
    Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
    Modeling of the Influence of Graded Element Matching Errors in CMOS Current-Steering DACs1999In: Proceedings of the 17th Norchip Conference, 1999Conference paper (Other academic)
    Abstract [en]

    In analog and mixed-mode circuits the matching between circuit elements is crucial.For example, in binary encoded digital-to-analog converters (DACs) the matchingbetween different bit weights can set the limit on the performance. Related to earlier workmodeling the influence of stochastic matching, the influence of graded element matching errorson the performance of current-steering DACs is shown. Presented are calculated results thatcorrelate very well with simulated results. As performance measures we use both static measuresas DNL and INL as well as frequency domain parameters as SNDR and SFDR. This discussioncan also be applied to other DAC structures, for example switched-capacitor.

  • 69.
    Andersson, Olof
    et al.
    Linköping University, Department of Physics, Chemistry and Biology, Complex Materials and Devices. Linköping University, Faculty of Science & Engineering.
    Maas, Joris
    Holst Ctr TNO, Netherlands.
    Gelinck, Gerwin
    Holst Ctr TNO, Netherlands; Eindhoven Univ Technol, Netherlands.
    Kemerink, Martijn
    Linköping University, Department of Physics, Chemistry and Biology, Biomolecular and Organic Electronics. Linköping University, Faculty of Science & Engineering.
    Scalable Electronic Ratchet with Over 10% Rectification Efficiency2020In: Advanced Science, E-ISSN 2198-3844, Vol. 7, no 3, article id 1902428Article in journal (Refereed)
    Abstract [en]

    Electronic ratchets use a periodic potential with broken inversion symmetry to rectify undirected (electromagnetic, EM) forces and can in principle be a complement to conventional diode-based designs. Unfortunately, ratchet devices reported to date have low or undetermined power conversion efficiencies, hampering applicability. Combining experiments and numerical modeling, field-effect transistor-based ratchets are investigated in which the driving signal is coupled into the accumulation layer via interdigitated finger electrodes that are capacitively coupled to the field effect transistor channel region. The output current-voltage curves of these ratchets can have a fill factor amp;gt;amp;gt; 0.25 which is highly favorable for the power output. Experimentally, a maximum power conversion efficiency well over 10% at 5 MHz, which is the highest reported value for an electronic ratchet, is determined. Device simulations indicate this number can be increased further by increasing the device asymmetry. A scaling analysis shows that the frequency range of optimal performance can be scaled to the THz regime, and possibly beyond, while adhering to technologically realistic parameters. Concomitantly, the power output density increases from approximate to 4 W m(-2) to approximate to 1 MW m(-2). Hence, this type of ratchet device can rectify high-frequency EM fields at reasonable efficiencies, potentially paving the way for actual use as energy harvester.

  • 70.
    Andersson, Oscar
    Linköping University, Department of Management and Engineering.
    Energikombinat i Halmstads fjärrvärmesystem2007Independent thesis Advanced level (degree of Magister), 20 points / 30 hpStudent thesis
    Abstract [sv]

    Klimatförändringar börjar allt mer få en viktig roll i allas vardag och för energibranschen har arbetet med att minska miljöpåverkan bara börjat. Branschen har sedan en tid tillbaka premierat fjärrvärme som bra miljöval för uppvärmningskälla för bostäder och lokaler. Faktum kvarstår dock att beroende på hur fjärrvärmesystemet ser ut så påverkar näten miljön olika. I denna rapport behandlas det lokala energibolaget Halmstads Energi och Miljös fjärrvärmesystem genom en optimering av systemkostnaden. Utifrån optimeringen studeras sedan skuggpriser, drift och miljöpåverkan för systemet. Studien behandlar även de stora fördelarna med att energibolaget samarbetar med en eventuellt kommande energikrävande industrier, i detta fall en etanolfabrik. I och med samarbetet bildas ett energikombinat där fjärrvärme, el och etanol tillverkas.

    För analysen används ett energisystemperspektiv som får större geografiska gränser än bara Halmstad. Undersökningen av systemet görs med hjälp av datorprogrammet MODEST som är ett energioptimeringsprogram som utvecklats på Linköpings Tekniska högskola. Modellen av Halmstads fjärrvärmenät baseras och valideras mot driftsäsongen 2005 och har visat sig stämma med verkligheten bra.

    Resultatet visar att Halmstad Energi och Miljö planerade effekthöjningar används fullt ut men att det nätet kommer få stora effekttoppar inom en snar framtid. Energikombinatet som analyseras visar sig både ha ekonomiska som miljöfördelar för både energibolaget och en etanolfabrik. Spillvärmen som kan utvinnas kan även den minska användningen av topplastanläggningarna i fjärrvärmenätet.

    Download full text (pdf)
    FULLTEXT01
  • 71.
    Andersson, Per-Oskar
    Linköping University, Department of Electrical Engineering.
    Rhapsody on small processor platforms2008Independent thesis Advanced level (professional degree), 20 credits / 30 HE creditsStudent thesis
    Abstract [en]

    Rhapsody is a Model-Driven Development (MDD) tool for embedded and real-time system design. The purpose of this thesis is to determine if Rhapsody can be used for software development on small processor platforms such as the Atmel AVR. Rhapsody is normally used on platforms running an operating system. Therefore certain adaptations are needed in order to use it on platforms without an operating system. These adaptations and their affect on the usability of the tool, advantages and disadvantages are all studied while porting AVR-software to Rhapsody on one of CC Systems products, the robust on-board computer CC Pilot XL II.

    Download full text (pdf)
    FULLTEXT01
  • 72.
    Andersson, Peter
    Linköping University, Department of Electrical Engineering.
    Design of a channel board used in an electronic warfare target simulator2006Independent thesis Advanced level (degree of Magister), 20 points / 30 hpStudent thesis
    Abstract [en]

    A channel board was designed for a DRFM circuit. The DRFM is implemented in a Virtex-4 FPGA from Xilinx. In the future a similar channel board is intended to be used for target echo generation in ELSI which is an electronic warfare simulator at Saab Bofors Dynamics in Linköping.

    Besides the DRFM circuit the channel board consists of analog-to-digital converters, digital-to-analog converters, Ethernet plug-in board with a microcontroller, voltage regulators, FPGA configuration memory, voltage amplifiers, current amplifiers, oscillator, buffers/drivers and bus transceivers. The sample rate is 200 MHz and LVDS signalling standard is used between the DRFM circuit and the converters.

    The channel board has a JTAG interface which enables in-system programming of the FPGA. This implies that the DRFM can easily be redesigned. An external computer can manage the channel board via Ethernet. Software was developed for the microcontroller on the channel board and for the external computer. The function of the channel board is heavily dependent on the DRFM circuit.

    The channel board design resulted in the assembly of a prototype circuit board. Measurements were performed in a lab and the channel board was approved to be integrated in ELSI for further tests.

    Download full text (pdf)
    FULLTEXT01
  • 73.
    Andersson, Peter
    Linköping University, Department of Electrical Engineering.
    Implementering av digitalt vågfilter av Richardstyp i FPGA2002Independent thesis Basic level (professional degree)Student thesis
    Abstract [en]

    Filtrets funktion efter implementeringen var samma som modellens byggd i Simulink. A Richards’ structure wave digital filter has been implemented on an evaluation board in an FPGA. Samples can be sent to the filter and received from the filter using the serial port of a computer. The method used is that a modell of the filter has been created in Simulink. The filter has been modified with respect to scaling, noise and stability. VHDL for the filter has been generated in Simulink by using Xilinx blockset to build the modell. Also, VHDL has been constructed to be able to send samples between the filter and the memory on the evaluationboard. For communication between the memory on the evaluationboard and the computer, existing solutions have been used. The functionality of the filter after implementation was the same as in the modell built in Simulink.

    Download full text (pdf)
    FULLTEXT01
  • 74.
    Andersson, Peter
    Linköping University, Department of Electrical Engineering.
    Överföring av digital video via FireWire2002Independent thesis Basic level (professional degree)Student thesis
    Abstract [en]

    Transmission of digital signals is today more frequently used than transmission of analog signals. One reason for this is that a digital signal is less sensitive to noise than an analog, another reason is that almost all signals today are handled in a digital format. This thesis describes the development of a system that receives digital video signals through FireWire. The standard for FireWire, which is a high performance serial bus, is under development. Today the standard of the bus supports transmission of data with a speed of up to 400 Mbit/s. In the future FireWire is supposed to transmit data with a speed of up to 3,2 Gbit/s. The thesis gives an introduction to the technique for FireWire and how it is implemented. It also includes a short description of digital video signals in DVCAM format.

    Download full text (pdf)
    FULLTEXT01
  • 75.
    Andersson, Pontus
    Linköping University, Department of Science and Technology.
    Visuell processreglering2007Independent thesis Basic level (degree of Bachelor), 10 points / 15 hpStudent thesis
    Abstract [sv]

    Examensarbetet handlar om att ta fram en processmodell för nivåreglering och det innehåller flera utmaningar. Vätskesystemets dynamik och balans måste beaktas likväl som lämpliga reglermetoder samt modellens utseende. I den här rapporten behandlas hela händelseförloppet från initialskedet till en färdig produkt redo att visas för en publik. Läsaren får möjlighet att närmare granska de komponenter som modellen är uppbyggd av, ta del av programmeringsarbetet och de omfattande test av modellen som utförts. Flera teknikområden belyses men fokus riktas särskilt på ABB:s styrsystem AC800M/800xA, fältbussteknik och reglerstrategier. PID-regulatorn har under arbetet spelat en stor roll och reglerstrategier som innefattar bl.a. framkoppling och kaskadkoppling analyseras och diskuteras. För att bedöma skillnader i val av reglermetod används grafer från praktiska försök. Rapportens upplägg med flertalet illustrationer och den genomgripande tekniska dokumentationen hjälper läsaren att förstå modellens funktion och uppbyggnad.

    Download full text (pdf)
    FULLTEXT01
  • 76.
    Andersson, Rikard
    et al.
    Linköping University, Department of Electrical Engineering, Vehicular Systems. Linköping University, Faculty of Science & Engineering.
    Garrido, Mario
    Univ Politecn Madrid, Spain.
    Using Rotator Transformations to Simplify FFT Hardware Architectures2020In: IEEE Transactions on Circuits and Systems Part 1: Regular Papers, ISSN 1549-8328, E-ISSN 1558-0806, Vol. 67, no 12, p. 4784-4793Article in journal (Refereed)
    Abstract [en]

    In this paper, we present a new approach to simplify fast Fourier transform (FFT) hardware architectures. The new approach is based on a group of transformations called decimation, reduction, center, move and merge. By combining them it is possible to transform the rotators at different FFT stages, move them to other stages and merge them in such a way that the resulting rotators are simpler than the original ones. The proposed approach can be combined with other existing techniques such coefficient selection and shift-and-add implementation, or rotator allocation in order to obtain low-complexity FFT hardware architectures. To show the effectiveness of the proposed approach, it has been applied to single-path delay feedback (SDF) FFT hardware architectures, where it is observed that the complexity of the rotators is reduced up to 33%.

  • 77.
    Andersson, Robby
    Linköping University, Department of Electrical Engineering.
    FPGA design of a controller for a CAN controller.2003Independent thesis Basic level (professional degree)Student thesis
    Abstract [en]

    This diploma work describes how an FPGA is designed to control a CAN controller. It describes the different tools used when working with Actel’s design tools and the sequence of work applied. It gives a short overview of a multiplexer, the CAN bus, an analog/digital-converter and some more information on the actual FPGA. It also brings up the design process of the FPGA, planning, coding, simulating, testing and finally programming the FPGA. The different parts implemented in the FPGA are a shift-register and two state- machines that are connected with each other. They work together to control the SJA1000 CAN controller made by Philips. They also receive data from the analog/digital-converter that they forward onwards to the CAN controller that forward the data on the CAN bus.

    Download full text (pdf)
    FULLTEXT01
  • 78.
    Andersson, Simon
    Linköping University, Department of Electrical Engineering, Vehicular Systems.
    Modeling and Control of Fuel Cell Stacks in Autonomous Underwater Vehicles2024Independent thesis Advanced level (degree of Master (Two Years)), 28 HE creditsStudent thesis
    Download full text (pdf)
    fulltext
  • 79. Order onlineBuy this publication >>
    Andersson, Stefan
    Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
    Multiband LNA Design and RF-Sampling Front-Ends for Flexible Wireless Receivers2006Doctoral thesis, comprehensive summary (Other academic)
    Abstract [en]

    The wireless market is developing very fast today with a steadily increasing number of users all around the world. An increasing number of users and the constant need for higher and higher data rates have led to an increasing number of emerging wireless communication standards. As a result there is a huge demand for flexible and low-cost radio architectures for portable applications. Moving towards multistandard radio, a high level of integration becomes a necessity and can only be accomplished by new improved radio architectures and full utilization of technology scaling. Modern nanometer CMOS technologies have the required performance for making high-performance RF circuits together with advanced digital signal processing. This is necessary for the development of low-cost highly integrated multistandard radios. The ultimate solution for the future is a software-defined radio, where a single hardware is used that can be reconfigured by software to handle any standard. Direct analog-to-digital conversion could be used for that purpose, but is not yet feasible due to the extremely tough requirements that put on the analog-to-digital converter (ADC). Meanwhile, the goal is to create radios that are as flexible as possible with today’s technology. The key to success is to have an RF front-end architecture that is flexible enough without putting too tough requirements on the ADC.

    One of the key components in such a radio front-end is a multiband multistandard low-noise amplifier (LNA). The LNA must be capable of handling several carrier frequencies within a large bandwidth. Therefore it is not possible to optimize the circuit performance for just one frequency band as can be done for a single application LNA. Two different circuit topologies that are suitable for multiband multistandard LNAs have been investigated, implemented, and measured. Those two LNA topologies are: (i) wideband LNAs that cover all the frequency bands of interest (ii) tunable narrowband LNAs that are tunable over a wide range of frequency bands.

    Before analog-to-digital conversion the RF signal has to be downconverted to a frequency manageable by the analog-to-digital converter. Recently the concept of direct sampling of the RF signal and discrete-time signal processing before analog-to-digital conversion has drawn a lot of attention. Today’s CMOS technologies demonstrate very high speeds, making the RF-sampling technique appealing in a context of multistandard operation at GHz frequencies. In this thesis the concept of RF sampling and decimation is used to implement a flexible RF front-end, where the RF signal is sampled and downconverted to baseband frequency. A discrete-time switched-capacitor filter is used for filtering and decimation in order to decrease the sample rate from a value close to the carrier frequency to a value suitable for analog-to-digital conversion. To demonstrate the feasibility of this approach an RF-sampling front-end primarily intended for WLAN has been implemented in a 0.13 μm CMOS process.

    List of papers
    1. A Tuned, Inductorless, Recursive Filter LNA in CMOS
    Open this publication in new window or tab >>A Tuned, Inductorless, Recursive Filter LNA in CMOS
    2002 (English)In: Proceedings of the European Solid-State Circuit Conference (ESSCIRC), Florens, Italy, September, 2002, p. 351-354Conference paper, Published paper (Refereed)
    Abstract [en]

    An active recursive filter approach is proposed for the implementation of an inductorless, tuned LNA in CMOS. Such an LNA was designed and fabricated ina 0.8 μm CMOS process. In simulation, the feasibility of this type of LNA was demonstrated, and reasonably good performance was obtained. The fabricated device shows a center frequency tuning range from 250 MHz to 975 MHz. Gain and Q value are tunable in a wide range. The LNA exhibits an input referred 1 dB compression point of -31 dB m and a noise figure of approximately 3 dB measured at 900 MHz center frequency.

    National Category
    Engineering and Technology
    Identifiers
    urn:nbn:se:liu:diva-14084 (URN)
    Conference
    28th European Solid-State Circuit Conference (ESSCIRC). Firenze, Italy, September 24-26, 2002.
    Available from: 2006-10-16 Created: 2006-10-16 Last updated: 2013-10-31
    2. An Active Recursive RF Filter in 0.35 μm BiCMOS
    Open this publication in new window or tab >>An Active Recursive RF Filter in 0.35 μm BiCMOS
    2005 (English)In: Journal of Analog Integrated Circuits and Signal Processing, ISSN 0925-1030, Vol. 44, no 3, p. 213-218Article in journal (Refereed) Published
    Abstract [en]

    An active recursive filter approach is proposed for the implementaion of an inductorless, tuneable RF filter in BiCMOS. A test circuit was designed and manufactured in a 0.35 μm SiGe BiCMOS technology. In simulations, the feasibility of this type of filter was demonstrated and reasonably good performance was obtained. The simulations show a center frequency tuning range from 6 to 9.4 GHz and a noise figure of 8.8 to 10.4 dB depending on center frequency. Gain and Q-value are tunable in a wide range. Simulated IIP-3 and 1-dB compression point is −26 and −34 dBm respectively, simulated at the center frequency 8.5 GHz and with 15 dB gain. Measurements on the fabricated device shows a center frequency tuning range from 6.6 to 10 GHz, i.e. slightly higher center frequencies were measured than the simulated.

    Keywords
    active filter, tuneable recursive filter for multicarrier systems, inductorless RF filter, tuneable gain and Q
    National Category
    Engineering and Technology
    Identifiers
    urn:nbn:se:liu:diva-14085 (URN)10.1007/s10470-005-3002-2 (DOI)
    Available from: 2006-10-16 Created: 2006-10-16 Last updated: 2013-10-31
    3. A 750 MHz to 3 GHz Tunable Narrowband Low-Noise Amplifier
    Open this publication in new window or tab >>A 750 MHz to 3 GHz Tunable Narrowband Low-Noise Amplifier
    2005 (English)In: Proceedings of the Norchip 2005 Conference, Oulu, Finland, 2005, p. 8-11Conference paper, Published paper (Refereed)
    Abstract [en]

    An active recursive filter approach is proposed for the implementation of an inductorless, tunable LNA in CMOS. A test circuit was designed and manufactured in a 0.18 μm CMOS technology. The feasibility of this type of LNA was demonstrated in both simulations and measurements and reasonably good performance was obtained. The measurements show a center frequency tuning range from 0.75-3 GHz and a minimum noise figure of 4.8 dB. Gain and Q value are also tunable in a wide range. Measured IIP-3 and 1-dB compression point is -24 dBm and -29.5 dBm respectively, measured at the center frequency 1.7 GHz and with 21 dB gain.

    Keywords
    CMOS integrated circuits, UHF amplifiers, active filters, circuit tuning, integrated circuit design, low noise amplifiers, recursive filters, CMOS technology, active recursive filter, inductorless low-noise amplifier, tunable narrowband low-noise amplifier
    National Category
    Engineering and Technology
    Identifiers
    urn:nbn:se:liu:diva-14086 (URN)10.1109/NORCHP.2005.1596976 (DOI)
    Available from: 2006-10-16 Created: 2006-10-16
    4. Wideband LNA for a Multistandard Wireless Receiver in 0.18 μm CMOS
    Open this publication in new window or tab >>Wideband LNA for a Multistandard Wireless Receiver in 0.18 μm CMOS
    2003 (English)In: Proceedings of the 29th European Solid-State Circuits Conference, 2003. ESSCIRC '03, 2003, p. 655-658Conference paper, Published paper (Refereed)
    Abstract [en]

    A differential wideband LNA for a multistandard receiver has been designed and implemented in 0.18μm CMOS. The circuit topology is a two-stage amplifier with active feedback. The input stage is a common-source stage with a common-drain stage in the feedback loop for impedance matching. Bandwidth enhancement with inductive shunt-peaking is used for maximizing the bandwidth. Measurements on the fabricated device show a power gain of 13.1 dB and a 3-dB bandwidth of nearly 7 GHz together with an IIP3 and a 1-dB compression point of -4.7 dBm and -15.2 dBm respectively. The measured noise figures are 3.3 dB at 1 GHz and 5.5 dB at 6 GHz. Reported LNAs with similar performance are usually implemented with bipolar transistors or MESFETs.

    Keywords
    CMOS integrated circuits, integrated circuit design, radio receivers, wideband amplifiers
    National Category
    Engineering and Technology
    Identifiers
    urn:nbn:se:liu:diva-14087 (URN)10.1109/ESSCIRC.2003.1257220 (DOI)0-7803-7995-0 (ISBN)
    Conference
    29th European Solid-State Circuits Conference, 2003. Estoril, Portugal, September 16-18.
    Available from: 2006-10-16 Created: 2006-10-16 Last updated: 2013-10-31
    5. Wideband LNA for aMultistandard RF-Sampling Front-End in 0.13 μm CMOS
    Open this publication in new window or tab >>Wideband LNA for aMultistandard RF-Sampling Front-End in 0.13 μm CMOS
    (English)Manuscript (Other academic)
    Abstract [en]

    The pad pitch of modern RF ICs is in order of few tens of micrometers. Connecting the large number of high speed I/Os to outside world with good signal fidelity and low cost is extremely challenging. To cope with this requirement, we need reflection-free transmission lines from on-chip pad to on-board SMA connectors. Such a transmission line is very hard to design due to the difference in on-chip and on-board feature size and the requirement for extremely large bandwidth. In this paper, we propose the use of narrow tracks close to chip and wide tracks away from the chip. This narrow to wide transition in width results in impedance discontinuity. A step change in substrate thickness is utilized to cancel the effect of the width discontinuity, thus achieving a reflection-free microstrip. To verify the concept several microstrips were designed on multilayer FR4 PCB without any additional manufacturing steps. The TDR measurements reveal that impedance variation is less then 3Ω for 50Ω microstrip when the width changes from 165μm to 940μm and substrate thickness changes from 100μm to 500μm. The Sparameter measurement on same microstrip shows S11 better then -9dB for the frequency range 1-6GHz

    National Category
    Engineering and Technology
    Identifiers
    urn:nbn:se:liu:diva-14088 (URN)
    Available from: 2006-10-16 Created: 2006-10-16 Last updated: 2018-10-08
    6. Channel length as a design parameter for low noise wideband LNAs in deep submicron CMOS technologies
    Open this publication in new window or tab >>Channel length as a design parameter for low noise wideband LNAs in deep submicron CMOS technologies
    2004 (English)In: Proceedings of the Norchip 2004 Conference, Oslo, Norway, November, 2004, p. 123-126Conference paper, Published paper (Refereed)
    Abstract [en]

    In this paper, measurements of drain thermal noise for three NMOS devices with different channel lengths was carried out. The three NMOS devices were all implemented in a 0.18 μm CMOS technology, with channel lengths 0.18. 0.36, and 0.72 μm, respectively. The result was then compared with simulated data using the BSIM3- model and parameters provided by the vendor Large discrepancies between measurements and simulations were observed. This work was done in order to understand how to utilize transistor length as a design parameter to achieve optimal noise gures for wideband LNAs in deep submicron technologies.

    Keywords
    CMOS, wideband LNAs
    National Category
    Engineering and Technology
    Identifiers
    urn:nbn:se:liu:diva-14089 (URN)10.1109/NORCHP.2004.1423838 (DOI)0-7803-8510-1 (ISBN)
    Available from: 2006-10-16 Created: 2006-10-16 Last updated: 2013-10-31
    7. SC Filter for RF Down Conversion with Wideband Image Rejection
    Open this publication in new window or tab >>SC Filter for RF Down Conversion with Wideband Image Rejection
    2006 (English)In: Proceedings of the ISCAS 2006 conference, Kos, Greece, 2006, p. 3542-3545Conference paper, Published paper (Refereed)
    Keywords
    SF filter, RF downconversion, RF sampling
    National Category
    Engineering and Technology
    Identifiers
    urn:nbn:se:liu:diva-14090 (URN)
    Available from: 2006-10-16 Created: 2006-10-16 Last updated: 2009-04-24
    8. SC Filter for RF Sampling and Downconversion with Wideband Image Rejection
    Open this publication in new window or tab >>SC Filter for RF Sampling and Downconversion with Wideband Image Rejection
    2006 (English)In: Journal of Analog Integrated Circuits and Signal Processing by Springer, special issue: MIXDES, ISSN 0925-1030, Vol. 49, no 2, p. 115-122Article in journal (Refereed) Published
    Abstract [en]

    In this paper we present an SC filter for RF downconversion using the direct RF sampling and decimation technique. The circuit architecture is generic and it features high image rejection for wideband signals and good linearity. An SC implementation in 0.13μm CMOS suitable for an RF of 2.4 GHz and 20 MHz signal bandwidth is presented as a demonstrator. Simulation results obtained using Cadence Spectre simulation tools are included.

    Keywords
    RF sampling, Decimation filter, SC filter, Wideband image rejection
    National Category
    Engineering and Technology
    Identifiers
    urn:nbn:se:liu:diva-14091 (URN)10.1007/s10470-006-7833-2 (DOI)
    Available from: 2006-10-16 Created: 2006-10-16
    9. Noise Analysis and Noise Estimation of an RF-Sampling Front-End using an SC Decimation Filter
    Open this publication in new window or tab >>Noise Analysis and Noise Estimation of an RF-Sampling Front-End using an SC Decimation Filter
    2006 (English)In: Proceedings of the MIXDES 2006 Conference, Gdynia, Poland, 2006, p. 343-348Conference paper, Published paper (Refereed)
    Keywords
    RF sampling, decimation, thermal- and 1/f-noise, SC filter
    National Category
    Engineering and Technology
    Identifiers
    urn:nbn:se:liu:diva-14092 (URN)
    Available from: 2006-10-16 Created: 2006-10-16 Last updated: 2009-04-24
    10. Multiband Direct RF-Sampling Receiver Front-End for WLAN in 0.13 μm CMOS
    Open this publication in new window or tab >>Multiband Direct RF-Sampling Receiver Front-End for WLAN in 0.13 μm CMOS
    (English)Manuscript (Other academic)
    Abstract [en]

    In this paper a flexible RF-sampling front-end primarily intended for WLAN operating in the 2.4 GHz and 5- 6 GHz bands is presented. The circuit is implemented in a 0.13 mum CMOS process with certain built-in test features. It consists of a wideband LNA and a SC discrete-time decimation filter used as a sampling IQ down-converter. The architecture is generic and scalable in frequency and it can operate at a sampling frequency up to 3 GHz and RF carrier up to 6 GHz. The decimation factor is 8 or 16 rendering the following A/D conversion feasible. The frequency response, linearity, and NF of the whole front-end have been measured. At the power consumption of 176 mW the circuit achieves specs that are satisfactory for WLAN applications.

    Identifiers
    urn:nbn:se:liu:diva-14093 (URN)10.1109/ECCTD.2007.4529563 (DOI)
    Available from: 2006-10-16 Created: 2006-10-16 Last updated: 2014-08-19
    Download full text (pdf)
    FULLTEXT01
  • 80.
    Andersson, Tobias
    et al.
    Linköping University, Department of Electrical Engineering.
    Wahlsten, Johan
    Linköping University, Department of Electrical Engineering.
    Delta-Sigma Modulation Applied to Switching RF Power Amplifiers2007Independent thesis Basic level (professional degree), 20 points / 30 hpStudent thesis
    Abstract [en]

    Background:

    The task of this thesis is to investigate the possibility of using non-linear high efficiency switching power amplifiers with spectrally efficient varying envelope modulation schemes and, if possible, further investigate such a solution on a high level.

    The thesis focuses on the theory necessary to understand the technical issues related to power amplifiers and the procedures behind simulating and measuring the characteristics of different power amplifier configurations. The thesis also covers basic theory behind Delta-Sigma-modulators. The theory is needed to draw conclusions about the feasibility of using a Delta-Sigma-modulator as input to a switching amplifier.

    Results:

    Using a Delta-Sigma-modulated input to a switching amplifier inherently degrades the performance, mainly because of poor coding efficiency and high switching activity. However, by merely using a switching amplifier as a mixer it is shown to be possible to transmit a non-constant envelope signal, with digital logic. The resulting circuit is, however, not an amplifier and it should not be seen as the final result. As already mentioned: the result lies in the investigation of a using Delta-Sigma-modulator as input to a switching amplifier.

    Conclusion:

    From this investigation we believe that the widely known technique: pulse width modulation (PWM), together with a tuned switching amplifier and some linearization technique, for example pre-distortion, is a better way to go. Much effort should be put in understanding the fundamental limits and possibilities of an efficient tuned switching power amplifier.

    Download full text (pdf)
    FULLTEXT01
  • 81.
    Andrén, Filip
    Linköping University, Department of Electrical Engineering, Automatic Control.
    Optimization of Random Access in 3G Long Term Evolution2009Independent thesis Advanced level (degree of Master (Two Years)), 20 credits / 30 HE creditsStudent thesis
    Abstract [en]

    Before a mobile can commence services it needs to have access to a base station. The access method is often referred to as random access (RA). One way to measure the performance of the RA procedure is the access delay (AD) of the mobiles, where AD is the time from which a mobile wants to start a RA attempt until it has received access.

    There are different approaches to optimize the RA procedure. Manual optimization is possible but costly. Automated optimization is preferable because of the lower costs and the possibility to change configuration fast in the base station when the operational conditions change. This thesis focuses on automated optimization of the RA procedure with regard to AD.

    A controllability and observability study of AD is first presented in this thesis. The controllability study shows that AD can be controlled by a number of RA parameters, whereas the observability study show that AD cannot always be correctly observed. The next part of this thesis presents a controller synthesis, where three different controllers are presented to control a specified percentile of AD. It is shown, through experiments, that the controllers derived can be used to optimize the RA procedure with regard to AD.

    Download full text (pdf)
    FULLTEXT01
  • 82.
    Angelov, Pavel
    Linköping University, Department of Electrical Engineering, Electronics System.
    Design of an Input Multiplexer for Video Applications2011Independent thesis Advanced level (degree of Master (Two Years)), 20 credits / 30 HE creditsStudent thesis
    Abstract [en]

    In modern home entertainment video systems the digital interconnection between the different components is becoming increasingly common. However, analog signal sources are still in widespread use and must be supported by new devices. In order to keep costs down, the digital and the analog receiver chains are implemented on a single die to form a system-on-chip (SoC). For such integrated circuits, it is beneficial to reduce the number of power supply domains to a minimum and preferably use the core voltage to power the analog circuits.

    An eight-to-one input multiplexer, targeted for video digitizer applications, is presented. Together with the multiplexer, a simple current-mode DC restoration circuit is provided. The goal has been to design the circuits for a standard, single-well, 65 nm CMOS process, entirely using low-voltage core transistors and a single 1.1 V supply domain, while allowing the input signal voltages to extend beyond the supply rails.

    To fulfill the requirements, a bootstrap technique has been proposed for the implementation of the multiplexer switches. Bootstrapping a CMOS switch allows high linearity, as well as wide bandwidth and dynamic range, to be achieved with a very low supply voltage. The simulated performance is: 3 dB bandwidth of 536 MHz with a 1.5 pF load at the output of the multiplexer and a SFDR of 65 dBc at 20 MHz and 1 Vp-p input signal. It has been verified that no transistor is stressed by high voltages, therefore, the circuit reliability is guaranteed. The DC restoration circuit utilizes the main video ADC, for measuring the DC level, and is capable of setting it with an accuracy of 60 μV within the range of 100 mV to 500 mV.

    Download full text (pdf)
    FULLTEXT03
  • 83.
    Angelov, Pavel
    et al.
    Linköping University, Department of Electrical Engineering, Integrated Circuits and Systems. Linköping University, Faculty of Science & Engineering.
    Nielsen Lönn, Martin
    Linköping University, Department of Electrical Engineering, Integrated Circuits and Systems. Linköping University, Faculty of Science & Engineering.
    A Fully Integrated Multilevel Synchronized-Switch-Harvesting-on-Capacitors Interface for Generic PEHs2020In: IEEE Journal of Solid-State Circuits, ISSN 0018-9200, E-ISSN 1558-173X, Vol. 55, no 8, p. 2118-2128Article in journal (Refereed)
    Abstract [en]

    This article presents a novel architecture for realizing the synchronized-switch-harvesting-on-capacitors (SSHC) technique used for enhanced energy extraction from piezoelectric transducers. The proposed architecture allows full integration by utilizing the storage capacitor already present in most energy-harvesting systems. A promising circuit implementation of the technique, named multilevel SSHC (ML-SSHC), is proposed as well, and its performance is analyzed theoretically. Based on that, a fully integrated and power-efficient transistor-level design in 0.18-mu m CMOS is presented and fabricated in a prototype chip. When operating at a mechanical excitation frequency of 22 Hz and delivering between 1.51 mu m and 4.82 mu W, the measured increase in extracted power is 7.01x and 6.71x, respectively, relative to an ideal full-bridge rectifier. While the performance is comparable to the state of the art, this is the first implementation allowing full integration at such low frequencies without posing special requirements on the piezoelectric harvester.

    Download full text (pdf)
    fulltext
  • 84.
    Angelov, Pavel
    et al.
    Linköping University, Department of Electrical Engineering, Integrated Circuits and Systems. Linköping University, Faculty of Science & Engineering.
    Nielsen Lönn, Martin
    Linköping University, Department of Electrical Engineering, Integrated Circuits and Systems. Linköping University, Faculty of Science & Engineering.
    Analysis of the capacitance-based multilevel bias flip rectifier for piezoelectric energy harvesting2019Report (Other academic)
    Abstract [en]

    This report presents the analysis of a novel capacitance-based multilevel bias flip rectifier used to increase the output power from a piezoelectric vibration energy harvesting system. The ideal voltage flipping efficiency is calculated based on the number of levels used followed by an analysis of the power losses caused by the bottom-plate parasitic capacitance of the flying capacitor used to distribute the charge between the levels. Then the time to complete the bias flip is examined and the difference between using either a diode or energy investment is investigated. This analysis is intended to be used for aiding in the design of such a system.

    Download full text (pdf)
    Analysis of the capacitance-based multilevel bias flip rectifier for piezoelectric energy harvesting
  • 85.
    Angelov, Pavel
    et al.
    Linköping University, Department of Electrical Engineering, Integrated Circuits and Systems. Linköping University, Faculty of Science & Engineering.
    Nielsen Lönn, Martin
    Linköping University, Department of Electrical Engineering, Integrated Circuits and Systems. Linköping University, Faculty of Science & Engineering.
    Alvandpour, Atila
    Linköping University, Department of Electrical Engineering, Integrated Circuits and Systems. Linköping University, Faculty of Science & Engineering.
    Ring-oscillator-based timing generator for ultralow-power applications2017In: 2017 IEEE NORDIC CIRCUITS AND SYSTEMS CONFERENCE (NORCAS): NORCHIP AND INTERNATIONAL SYMPOSIUM OF SYSTEM-ON-CHIP (SOC), IEEE , 2017Conference paper (Refereed)
    Abstract [en]

    Many integrated circuit functional blocks, such as data and power converters, require timing and control signals consisting of complex sequences of pulses. Traditionally, these signals are generated from a clock signal using a combination of flip-flops, latches and delay elements. Due to the large internal switching activity of flips-flops and due to the many, effectively unused, clock cycles, this solution is inefficient from a power consumption point of view and is, therefore, unsuitable for ultralow-power applications. In this paper we present a method to generate non-overlapping control signals without using flip-flops or a clock. We propose to decode and translate the internal states of a ring oscillator into the desired control signal sequence. We show how this can be achieved using a simple combinatorial logic decoder. The proposed architecture significantly reduces the switching activity and the capacitive load, largely reducing the consumed power. We show an example implementation of a 9-bit SAR logic utilizing our proposed method. Furthermore, we show simulation results and compare the power consumption of the example SAR implementation to that of a functionally identical flip-flop-based state-of-the-art ultralow-power SAR. We were able to achieve a 5.8x reduction in consumed power for the complete SAR and 8x for the one-hot generation sub-part.

  • 86.
    Antelius, Henrik
    Linköping University, Department of Electrical Engineering.
    Retargeting a C Compiler for a DSP Processor2004Independent thesis Basic level (professional degree)Student thesis
    Abstract [en]

    The purpose of this thesis is to retarget a C compiler for a DSP processor.

    Developing a new compiler from scratch is a major task. Instead, modifying an existing compiler so that it generates code for another target is a common way to develop compilers for new processors.

    This is called retargeting. This thesis describes how this was done with the LCC C compiler for the Motorola DSP56002 processor.

    Download full text (pdf)
    FULLTEXT01
  • 87.
    Anton, Gagner
    et al.
    Linköping University, Department of Science and Technology, Physics and Electronics. Linköping University, The Institute of Technology.
    Hebib, Nino
    Linköping University, Department of Science and Technology, Physics and Electronics. Linköping University, The Institute of Technology.
    FPGA Software Development for Control Purposes of High-Frequency Switching Power Converters2016Independent thesis Advanced level (degree of Master (Two Years)), 20 credits / 30 HE creditsStudent thesis
    Abstract [en]

    FPGA stands for Field Programmable Gate Array and it is a technology that has been on the rise the last decades. With a decrease in size of the logic elements commercially available products have started to have more built-in functionality in one package and by being reprogrammable makes the system a powerful competitor among its neighbors. FPGA technology in comparison with Digital Signal Processing technology is generally interesting because of the parallelism of the programming that can be made. This allows for more operations in less time. In this thesis a system is developed to control power converters with control signals in high frequency. A previous project is used as a base and a toolchain of new components are implemented to create a new, more generic system. The previous system is evaluated and a new protocol for communication is developed. The toolchain with the necessary control blocks is implemented in Quartus II that includes a timer block, a pulse width modulation block, a PID controller block and a FIR-filter block. The system is used to control a power converter and the result is evaluated.

    Download full text (pdf)
    FPGA Software Development for Control Purposes of High-Frequency Switching Power Converters
  • 88.
    Arbring, Joel
    et al.
    Linköping University, Department of Electrical Engineering, Information Coding.
    Hedström, Patrik
    Linköping University, Department of Electrical Engineering, Information Coding.
    On Data Compression for TDOA Localization2010Independent thesis Advanced level (professional degree), 20 credits / 30 HE creditsStudent thesis
    Abstract [en]

    This master thesis investigates different approaches to data compression on common types of signals in the context of localization by estimating time difference of arrival (TDOA). The thesis includes evaluation of the compression schemes using recorded data, collected as part of the thesis work. This evaluation shows that compression is possible while preserving localization accuracy.

    The recorded data is backed up with more extensive simulations using a free space propagation model without attenuation. The signals investigated are flat spectrum signals, signals using phase-shift keying and single side band speech signals. Signals with low bandwidth are given precedence over high bandwidth signals, since they require more data in order to get an accurate localization estimate.

    The compression methods used are transform based schemes. The transforms utilized are the Karhunen-Loéve transform and the discrete Fourier transform. Different approaches for quantization of the transform components are examined, one of them being zonal sampling.

    Localization is performed in the Fourier domain by calculating the steered response power from the cross-spectral density matrix. The simulations are performed in Matlab using three recording nodes in a symmetrical geometry.

    The performance of localization accuracy is compared with the Cramér-Rao bound for flat spectrum signals using the standard deviation of the localization error from the compressed signals.

    Download full text (pdf)
    FULLTEXT01
  • 89.
    Armgarth, Astrid
    et al.
    Linköping University, Department of Science and Technology, Laboratory of Organic Electronics. Linköping University, Faculty of Science & Engineering. RISE Res Inst Sweden AB, Sweden.
    Pantzare, Sandra
    RISE Res Inst Sweden AB, Sweden.
    Arven, Patrik
    J2 Holding AB, Sweden.
    Lassnig, Roman
    RISE Res Inst Sweden AB, Sweden.
    Jinno, Hiroaki
    RIKEN, Japan; Univ Tokyo, Japan.
    Gabrielsson, Erik
    Linköping University, Department of Science and Technology, Laboratory of Organic Electronics. Linköping University, Faculty of Science & Engineering.
    Kifle, Yonatan Habteslassie
    Linköping University, Department of Electrical Engineering, Integrated Circuits and Systems. Linköping University, Faculty of Science & Engineering.
    Cherian, Dennis
    Linköping University, Department of Science and Technology, Laboratory of Organic Electronics. Linköping University, Faculty of Science & Engineering.
    Arbring Sjöström, Theresia
    Linköping University, Department of Science and Technology, Laboratory of Organic Electronics. Linköping University, Faculty of Science & Engineering.
    Berthou, Gautier
    Res Inst Sweden AB, Sweden.
    Dowling, Jim
    Res Inst Sweden AB, Sweden; KTH Royal Inst Technol, Sweden.
    Someya, Takao
    RIKEN, Japan; Univ Tokyo, Japan.
    Wikner, Jacob
    Linköping University, Department of Electrical Engineering, Integrated Circuits and Systems. Linköping University, Faculty of Science & Engineering.
    Gustafsson, Göran
    RISE Res Inst Sweden AB, Sweden.
    Simon, Daniel
    Linköping University, Department of Science and Technology, Laboratory of Organic Electronics. Linköping University, Faculty of Science & Engineering.
    Berggren, Magnus
    Linköping University, Department of Science and Technology, Laboratory of Organic Electronics. Linköping University, Faculty of Science & Engineering.
    A digital nervous system aiming toward personalized IoT healthcare2021In: Scientific Reports, E-ISSN 2045-2322, Vol. 11, no 1, article id 7757Article in journal (Refereed)
    Abstract [en]

    Body area networks (BANs), cloud computing, and machine learning are platforms that can potentially enable advanced healthcare outside the hospital. By applying distributed sensors and drug delivery devices on/in our body and connecting to such communication and decision-making technology, a system for remote diagnostics and therapy is achieved with additional autoregulation capabilities. Challenges with such autarchic on-body healthcare schemes relate to integrity and safety, and interfacing and transduction of electronic signals into biochemical signals, and vice versa. Here, we report a BAN, comprising flexible on-body organic bioelectronic sensors and actuators utilizing two parallel pathways for communication and decision-making. Data, recorded from strain sensors detecting body motion, are both securely transferred to the cloud for machine learning and improved decision-making, and sent through the body using a secure body-coupled communication protocol to auto-actuate delivery of neurotransmitters, all within seconds. We conclude that both highly stable and accurate sensing-from multiple sensors-are needed to enable robust decision making and limit the frequency of retraining. The holistic platform resembles the self-regulatory properties of the nervous system, i.e., the ability to sense, communicate, decide, and react accordingly, thus operating as a digital nervous system.

    Download full text (pdf)
    fulltext
  • 90.
    Arshad, Sana
    et al.
    NED University of Engn and Technology, Pakistan.
    Ramzan, Rashad.
    United Arab Emirates University, U Arab Emirates.
    Zafar, Faiza
    NED University of Engn and Technology, Pakistan.
    Wahab, Qamar-Ul
    Linköping University, Department of Physics, Chemistry and Biology. Linköping University, Faculty of Science & Engineering. NED Univ Engn and Technol, Dept Elect Engn, Pakistan.
    Highly Linear Inductively Degenerated 0.13 mu m CMOS LNA using FDC Technique2014In: 2014 IEEE ASIA PACIFIC CONFERENCE ON CIRCUITS AND SYSTEMS (APCCAS), IEEE , 2014, p. 225-228Conference paper (Refereed)
    Abstract [en]

    In this paper, a highly linear, inductively degenerated, common source narrowband LNA is presented. An extremely simple feed-forward distortion circuit (FDC) which consists of an appropriately sized ac-coupled diode connected NMOS is proposed. This circuit generates distortion components at output, when added at the input node as a feed forward element (M-6). These distortion components partially cancel the 3rd order nonlinearity of the cascode pair (M-2 and M-3), thus improving the overall linearity of LNA. The prototype is manufactured in standard 0.13 mu m CMOS process from IBM. Simulation and partial measurement results show the S11 and S22 to be -19.27dB and -7.14dB respectively at 2.45GHz. The simulation results of the LNA demonstrate a power gain of 18.5dB, NF of 4.38dB, input referred 1dBCP of -11.76dBm and IIP3 of +0.7dBm consuming 27.7mA from 1.0V power supply. The proposed LNA achieves the best input referred IIP3 reported in recent literature using 0.13 mu m CMOS in 2.4GHz frequency band.

  • 91.
    Arvidsson, Amanda
    Linköping University, Department of Science and Technology, Physics and Electronics. Linköping University, The Institute of Technology.
    Generic Control of Permanent Magnet Synchronous Motors2014Independent thesis Advanced level (degree of Master (Two Years)), 20 credits / 30 HE creditsStudent thesis
    Abstract [en]

    -

    Download full text (pdf)
    fulltext
  • 92. Order onlineBuy this publication >>
    Arwidson, Jonas
    Linköping University, Department of Science and Technology, Physics and Electronics. Linköping University, The Institute of Technology.
    Thermal Fatigue Life Prediction of Solder Joints in Avionics by Surrogate Modeling: A Contribution to Physics of Failure in Reliability Prediction2013Doctoral thesis, comprehensive summary (Other academic)
    Abstract [en]

    Manufacturers of aerospace, defense, and high performance (ADHP) equipment are currently facing multiple challenges related to the reliability of electronic systems. The continuing reduction in size of electronic components combined with increasing clock frequencies and greater functionality, results in increased power density. As an effect, controlling the temperature of electronic components is central in electronic product development in order to maintain and potentially improve the reliability of the equipment. Simultaneously, the transition to lead-free electronic equipment will most probably propagate also to the ADHP industry. Compared to well-proven tin-lead solder, the knowledge about field operation reliability of lead-free solders is still limited, as well as the availability of damage evaluation models validated for field temperature conditions. Hence, the need to fill in several knowledge gaps related to reliability and reliability prediction of lead-free solder alloys is emphasized. Having perceived increasing problems experienced in the reliability of fielded equipment, the ADHP industry has suggested inclusion of physics-of-failure (PoF) in reliability prediction of electronics as one potential measure to improve the reliability of the electronic systems.

    This thesis aims to contribute to the development of reliable ADHP systems, with the main focus on electronic equipment for the aerospace industry. In order to accomplish this, the thesis provides design guidelines for power distribution on a double-sided printed circuit board assembly (PBA) as a measure to improve the thermal performance without increasing the weight of the system, and a novel, computationally efficient method for PoF-based evaluation of damage accumulation in solder joints in harsh, non-cyclic field operation temperature environments.

    Thermal fatigue failure mechanisms and state‑of‑the‑art thermal design and design tools are presented, with focus on the requirements that may arise from avionic use, such as low weight, high reliability, and ability to sustain functional during high vibration levels and high g-forces. Paper I, II, and III describes an in-depth investigation that has been performed utilizing advanced thermal modeling of power distribution on a double-sided PBA as a measure to improve the thermal performance of electronic modules.

    Paper IV contributes to increasing the accuracy of thermal fatigue life prediction in solder joints, by employing existing analytical models for predicting thermal fatigue life, but enhancing the prediction result by incorporating advanced thermal analysis in the procedure.

    Papers V and VI suggest and elaborate on a computational method that utilizes surrogate stress and strain modeling of a solder joint, to quickly evaluate the damage accumulated in a critical solder joint from non-cyclic, non-simplified field operation temperature profiles, with accuracy comparable to finite element modeling. The method has been tested on a ball grid array package with SnAgCu solder joints. This package is included in an extensive set of accelerated tests that helps to qualify certain packages and solder alloys for avionic use. The tests include -20°C to +80°C and -55°C to +125°C thermal cycling of a statistically sound population of a number of selected packages, assembled with SnAgCu, Sn100C, and SnPbAg solder alloys. Statistical analysis of the results confirms that the SnAgCu-alloy may outperform SnPbAg solder at moderate thermal loads on the solder joints.

    In Papers VII and VIII, the timeframe is extended to a future, in which validated life prediction models will be available, and the suggested method is expected to increase the accuracy of embedded prognostics of remaining useful thermal fatigue life of a critical solder joint.

    The key contribution of the thesis is the added value of the proposed computational method utilized in the design phase for electronic equipment. Due to its ability for time-efficient operation on uncompressed temperature data, the method gives contribution to the accuracy, and thereby also to the credibility, of reliability prediction of electronic packages in the design phase. This especially relates to applications where thermal fatigue is a dominant contributor to the damage of solder joints.

    List of papers
    1. CFD Analysis of an Avionic Module for Evaluating Power Distribution as a Thermal Management Measure for a Double-sided PCB
    Open this publication in new window or tab >>CFD Analysis of an Avionic Module for Evaluating Power Distribution as a Thermal Management Measure for a Double-sided PCB
    2007 (English)In: Semiconductor Thermal Measurement and Management Symposium, SEMI-THERM 2007, IEEE , 2007, p. 233-243Conference paper, Published paper (Refereed)
    Abstract [en]

    Thermal design aspects of an avionic module including fully populated PCBs housed in a sealed enclosure have been studied by means of computational fluid dynamics. Effect of power distribution between the sides of a double-sided PCB on the case temperature of surface-mounted components has been investigated within a proposed simulation strategy. Simulation-based guidelines have been developed for thermal design of avionic modules, regarding preferable power configuration on a double-sided PCB, representing an alternative approach to thermal management, as compared to introducing additional cooling devices.

    Place, publisher, year, edition, pages
    IEEE, 2007
    Series
    Semiconductor Thermal Measurement and Management Symposium, ISSN 1065-2221 ; 2007
    Keywords
    Avionics, thermal management, double-sided PCB, CFD, non-dominated designs
    National Category
    Other Electrical Engineering, Electronic Engineering, Information Engineering
    Identifiers
    urn:nbn:se:liu:diva-91902 (URN)10.1109/STHERM.2007.352429 (DOI)1-4244-09589-4 (print) (ISBN)1-4244-09589-4 (online) (ISBN)
    Conference
    23rd Annual IEEE Semiconductor Thermal Measurement and Management Symposium (SEMI-THERM 2007), March 18-22, San Jose, CA. USA
    Note

    At the time for thesis presentation publication was in status: Manuscript

    Available from: 2013-05-04 Created: 2013-05-04 Last updated: 2016-12-22Bibliographically approved
    2. An experimental setup for validating a CFD model of a double-sided PCB in a sealed enclosure at various power configurations
    Open this publication in new window or tab >>An experimental setup for validating a CFD model of a double-sided PCB in a sealed enclosure at various power configurations
    2005 (English)In: Proceedings of EuroSime 2005, Berlin: EuroSime , 2005, p. 127-133Conference paper, Published paper (Refereed)
    Abstract [en]

    A flexible experimental setup enabling power control of a fully populated double-sided PCB has been realized, and is described in detail. A CFD model of a double-sided PCB housed in a sealed enclosure has been validated in a 19°C environment by means of temperature and flow measurement. The difference between simulated and measured component temperatures has been within 10%. Potential errors both in the model and in the experiments have been discussed and their impact on temperatures has been numerically evaluated.

    Place, publisher, year, edition, pages
    Berlin: EuroSime, 2005
    National Category
    Engineering and Technology
    Identifiers
    urn:nbn:se:liu:diva-28747 (URN)10.1109/ESIME.2005.1502787 (DOI)13922 (Local ID)0-7803-9062-8 (ISBN)0-7803-9063-6 (ISBN)13922 (Archive number)13922 (OAI)
    Conference
    The 6th IEEE EuroSimE conference, April 18-20, Berlin, Germany
    Available from: 2009-10-09 Created: 2009-10-09 Last updated: 2013-11-12Bibliographically approved
    3. Investigating the effect of power distribution on cooling a double-sided PCB: Numerical simulation and experiment
    Open this publication in new window or tab >>Investigating the effect of power distribution on cooling a double-sided PCB: Numerical simulation and experiment
    2005 (English)In: Proceedings of ASME Summer Heat Transfer Conference 2005, San Fransisco: ASME , 2005, p. 649-657Conference paper, Published paper (Refereed)
    Abstract [en]

    An experimental procedure for investigating the effect of power distribution on the cooling of a double-sided PCB is implemented. A number of computational fluid dynamics (CFD) models are validated by laboratory experiments performed in 19.5°C temperature environment. Case temperatures of surface-mounted components fully populating the PCB sides are measured and monitored in simulations. Different combinations of power distribution with other cooling methods, such as a heatsink tooled on a sealed or open enclosure, at natural or forced convection, are studied. Thermally efficient uniform and non-uniform power configurations are determined on a double sided PCB. It is concluded that managing power distribution on a double-sided PCB can be considered as a measure to improve the thermal performance of electronic modules.

    Place, publisher, year, edition, pages
    San Fransisco: ASME, 2005
    National Category
    Engineering and Technology
    Identifiers
    urn:nbn:se:liu:diva-28748 (URN)10.1115/HT2005-72549 (DOI)13923 (Local ID)0-7918-4734-9 (ISBN)0-7918-3762-9 (ISBN)13923 (Archive number)13923 (OAI)
    Conference
    ASME 2005 Summer Heat Transfer Conference collocated, with the ASME 2005 Pacific Rim Technical Conference and Exhibition on Integration and Packaging of MEMS, NEMS, and Electronic Systems, Heat Transfer: Volume 4, San Francisco, California, USA, July 17–22, 2005
    Available from: 2009-10-09 Created: 2009-10-09 Last updated: 2013-11-12Bibliographically approved
    4. On thermomechanical durability analysis combined with computational fluid dynamics thermal analysis
    Open this publication in new window or tab >>On thermomechanical durability analysis combined with computational fluid dynamics thermal analysis
    Show others...
    2007 (English)In: Proceedings of IMECE2007: ASME International Mechanical Engineering Congress and Exposition, American Society of Mechanical Engineers , 2007, p. 233-240Conference paper, Published paper (Refereed)
    Abstract [en]

    Results are presented on durability analysis of an electronic module subjected to thermal and power cycles, and vibration. A hierarchical analysis process for analyzing the durability of the module is described. The initial step is a transient thermal analysis of the unit in which the module is located. The three operating modes of the unit are modeled and analyzed using a commercially available computational fluid dynamics (CFD) tool. The tool generates a time history of the temperature at all points within the unit and module.

    The second step comprises exporting temperatures from the transient temperature analysis to a durability prediction tool. The temperatures calculated by the global analysis are mapped to the printed wiring assembly (PWA) mounted within the box, yielding the temperature distribution of the PWA as functions of time. The durability tool utilizes a modified Coffin Manson formula together with the transient temperature profile to estimate the durability of each lead and solder joint included in the module. Thermomechanical fatigue level of leads and solder joints within the unit are reported as a cumulative damage index (CDI). The CDI is the ratio of the number of cycles required for the test item to endure under a life time to the number of cycles the item is predicted to sustain before failure.

    Durability analysis of solder joint due to vibration is performed separately. The environment is specified according to the location where the unit is mounted. CDI due to vibration is added to form an overall CDI based on Miner’s rule.

    Place, publisher, year, edition, pages
    American Society of Mechanical Engineers, 2007
    Keywords
    Durability analysis, thermal cycling, vibration, transient power dissipation
    National Category
    Other Electrical Engineering, Electronic Engineering, Information Engineering
    Identifiers
    urn:nbn:se:liu:diva-91897 (URN)0791842991 (ISBN)
    Conference
    ASME International Mechanical Engineering Congress and Exposition (IMECE 2007), November 11–15, 2007, Seattle, Washington, USA
    Available from: 2013-05-04 Created: 2013-05-04 Last updated: 2013-12-03Bibliographically approved
    5. A computational method for evaluating the damage in a solder joint of an electronic package subjected to thermal loads
    Open this publication in new window or tab >>A computational method for evaluating the damage in a solder joint of an electronic package subjected to thermal loads
    (English)Manuscript (preprint) (Other academic)
    Abstract [en]

    Purpose – The purpose of this paper is to introduce a novel computational method to evaluate damage accumulation in a solder joint of an electronic package, when exposed to operating temperature environment. A procedure to implement the method is suggested, and a discussion of the method and its possible applications is provided in the paper.

    Originality/value – The method enables increased accuracy in thermal fatigue life prediction of solder joints. Combined with other failure mechanisms, it may contribute to the accuracy of reliability assessment of electronic packages.

    Design/methodology/approach – Methodologically, interpolated response surfaces based on specially designed finite element simulation runs, are employed to compute a damage metric at regular time intervals of an operating temperature profile. The developed method has been evaluated on a finite-element model of a lead-free PBGA256 package, and accumulated creep strain energy density has been chosen as damage metric.

    Findings – The method has proven to be two orders of magnitude more computationally efficient compared to finite element simulation. A general agreement within 3% has been found between the results predicted with the new method, and finite element simulations when tested on a number of temperature profiles from an avionic application. The solder joint temperature ranges between +25°C and +75°C.

    Practical implications – The method can be implemented as part of reliability assessment of electronic packages in the design phase.

    Keywords
    Computational method, electronic package, finite element analysis, thermal fatigue, operating temperature environment, lead-free solder
    National Category
    Other Electrical Engineering, Electronic Engineering, Information Engineering
    Identifiers
    urn:nbn:se:liu:diva-91898 (URN)
    Available from: 2013-05-04 Created: 2013-05-04 Last updated: 2013-05-08Bibliographically approved
    6. Investigation on thermal fatigue of SnAgCu, Sn100C, and SnPbAg solder joints in varying temperature environments
    Open this publication in new window or tab >>Investigation on thermal fatigue of SnAgCu, Sn100C, and SnPbAg solder joints in varying temperature environments
    Show others...
    (English)Manuscript (preprint) (Other academic)
    Abstract [en]

    Thermal cycling tests have been performed for a range of electronic components intended for avionic applications, assembled with SAC305, SN100C and SnPbAg solder alloys. Two temperature profiles have been used, the first ranging between -20°C to +80°C (TC1), and the second between -55°C and +125°C (TC2). High level of detail is provided for the solder alloy composition and the component package dimensions, and statistical analysis, partially supported by FE modeling, is reported. The test results confirm the feasibility of SAC305 as a replacement for SnPbAg under relatively benign thermomechanical loads. Furthermore, the test results serve as a starting point for estimation of damage accumulation in a critical solder joint in field conditions, with increased accuracy by avoiding data reduction. A computationally efficient method that was earlier introduced by the authors and tested on relatively mild temperature environments has been significantly improved to become applicable on extended temperature range, and it has been applied to a PBGA256 component with SAC305 solder in TC1 conditions. The method, which utilizes interpolated response surfaces generated by finite element modeling, extends the range of techniques that can be employed in the design phase to predict thermal fatigue of solder joints under field temperature conditions.

    Keywords
    Thermal cycling tests, lead-free solder, reliability prediction, surrogate modeling
    National Category
    Other Electrical Engineering, Electronic Engineering, Information Engineering
    Identifiers
    urn:nbn:se:liu:diva-91899 (URN)
    Available from: 2013-05-04 Created: 2013-05-04 Last updated: 2013-05-08Bibliographically approved
    7. Prognostics of Thermal Fatigue Failure of Solder Joints in Avionic Equipment
    Open this publication in new window or tab >>Prognostics of Thermal Fatigue Failure of Solder Joints in Avionic Equipment
    2012 (English)In: IEEE Aerospace and Electronic Systems Magazine, ISSN 0885-8985, E-ISSN 1557-959X, Vol. 27, no 4, p. 16-24Article in journal (Refereed) Published
    Abstract [en]

    A practical method has been suggested for solder joint thermal fatigue prognostics, which enables real-time fatigue calculations based on uncompressed temperature data embedded in a host system that performs safety-critical operations. The accuracy of the prognosticated remaining useful life depends on the level of details captured in the model, and the level of confidence from validation efforts.

    Place, publisher, year, edition, pages
    IEEE, 2012
    Keywords
    Thermal fatigue prognostics, physics-of-failure, electronics, avionics, solder joints.
    National Category
    Other Electrical Engineering, Electronic Engineering, Information Engineering
    Identifiers
    urn:nbn:se:liu:diva-91900 (URN)10.1109/MAES.2012.6203714 (DOI)
    Available from: 2013-05-04 Created: 2013-05-04 Last updated: 2017-12-06Bibliographically approved
    8. An approach to life consumption monitoring of solder joints in operating temperature environment
    Open this publication in new window or tab >>An approach to life consumption monitoring of solder joints in operating temperature environment
    2012 (English)In: Thermal, Mechanical and Multi-Physics Simulation and Experiments in Microelectronics and Microsystems (EuroSimE), 2012, IEEE , 2012, p. 1-8Conference paper, Published paper (Refereed)
    Abstract [en]

    This paper elaborates the 3T-approach to life consumption monitoring of solder joints in operating temperature environment without requiring simplification of operating loads.

    An overview of the 3T-approach is provided including assumptions made for a proposed realization in an avionic application. Associated implementation routines are highlighted and exemplified for a lead-free PBGA256 package with creep strain energy density (SEDcr) as damage metric.

    Factors that affect the prediction accuracy are investigated. A data resolution has been determined that delivers response surfaces that provide results comparable to 3-D finite-element (FE) simulations, while bearing two orders of magnitude higher computational efficiency.

    A stress-free temperature modification routine is proposed and proves to further mitigate accuracy problems.

    Place, publisher, year, edition, pages
    IEEE, 2012
    Keywords
    Life consumption monitoring, solder joints, avionics, thermal fatigue
    National Category
    Other Electrical Engineering, Electronic Engineering, Information Engineering
    Identifiers
    urn:nbn:se:liu:diva-91901 (URN)10.1109/ESimE.2012.6191699 (DOI)978-1-4673-1512-8 (ISBN)
    Conference
    13th International Conference on Thermal, Mechanical and Multi-Physics Simulation and Experiments in Microelectronics and Microsystems (EuroSimE 2012), April 16-18, Cascais, Portugal
    Available from: 2013-05-04 Created: 2013-05-04 Last updated: 2013-05-20Bibliographically approved
    Download full text (pdf)
    Thermal Fatigue Life Prediction of Solder Joints in Avionics by Surrogate Modeling: A Contribution to Physics of Failure in Reliability Prediction
    Download (pdf)
    omslag
  • 93.
    Arya, Ishan
    et al.
    Linköping University, Department of Electrical Engineering, Integrated Circuits and Systems.
    Sundaram, Viswanaath
    Linköping University, Department of Electrical Engineering, Integrated Circuits and Systems.
    A System Study Of Ultrasonic Transceivers For Haptic Applications2018Independent thesis Advanced level (degree of Master (Two Years)), 20 credits / 30 HE creditsStudent thesis
    Abstract [en]

    We are investigating the use of ultrasound in Haptic applications. Initially abrief background of ultrasonic transducers and its characteristics were presented.Then a theoretical research was documented to understand the concepts that govern haptics. This section also discusses the algorithm adopted by various researches to implement haptics in the professional world. Then investigations were made to understand the behavior of ultrasonic transducers and conduct soft-ware simulations to obtain various results. At first simulations were conducted on Field II software. This simulations involved the creation of elements in trans-ducers, transducer’s spatial impulse responses, transducer’s impulse responsein time and frequency domain, effect of adding apodization to the transducers,pulse echo response of the transducers, beam profile variation along the focallength of the transducers. Then a Matlab based GUI was used to study the relationship between number of elements in transducers, the frequency of the input signal and duty cycle variation of the input wave. A concept of phase shift, which explains the time delay generation was also coded in Matlab.

    Download full text (pdf)
    fulltext
  • 94.
    Asghar, Malik Summair
    Linköping University, Department of Electrical Engineering. Linköping University, The Institute of Technology.
    A “Divide-by-Odd Number” Injection-Locked Frequency Divider.2013Independent thesis Advanced level (degree of Master (Two Years)), 20 credits / 30 HE creditsStudent thesis
    Abstract [en]

    The use of resonant CMOS frequency dividers with direct injection in frequencysynthesizers has increased in recent years due to their lower power consumptioncompared to conventional digital prescalers. The theoretical and experimentalaspects of these dividers have received great attention. This masters thesis workis a continuation of earlier work, based on the fundamentals of Injection-LockedFrequency Dividers (ILFD’s). The LC CMOS ILFD with direct injection is wellknownfor its divide-by-2 capability. However, it does not divide well by oddnumbers. The goal of this master thesis work is to modify the LC CMOS ILFDwith direct injection so that it can divide equally well by odd and even integers.In this master thesis report, an introduction to the basic concepts behindInjection-Locked frequency dividers is first presented. Some of the previous workand the background of a reference LC CMOS ILFD design are studied. The author,studied the reference design, and the experimental setup used for characterizingit’s locking behavior. The algorithm used to characterize the locking behavior ofthis ILFD are explored to reproduce the results for divide-by-even numbers for theexisting ILFD topology. Using a Spice model these results are also reproduced insimulations.Over the years, numerous ILFD circuit topologies have been proposed, most ofwhich have been optimized for division by even numbers, especially divide-by-2.It has been more difficult to realize division by odd numbers, such as divide-by-3.This master thesis work develops a simple modification to an LC CMOS injectionlocked frequency divider (ILFD) with direct injection, which gives it a wide lockingrange both in the “divide-by-odd number” mode and in the conventional “divideby-even number” regime, thereby opening up applications which require frequencydivision by an odd number. The work presents the circuit architecture, SPICEsimulations and experimental validation.

    Download full text (pdf)
    ex-jobb_4653
  • 95.
    Asghar, Rizwan
    et al.
    Linköping University, Department of Electrical Engineering, Computer Engineering. Linköping University, The Institute of Technology.
    Liu, Dake
    Linköping University, Department of Electrical Engineering, Computer Engineering. Linköping University, The Institute of Technology.
    2-D Realization of WiMAX Channel Interleaver for Efficient Hardware Implementation2009In: Proceedings of World Academy of Science, Engineering and Technology (ISSN: 2070-3740), 2009, p. 25-29Conference paper (Refereed)
    Abstract [en]

    The direct implementation of interleaver functions in WiMAX is not hardware efficient due to presence of complex functions. Also the conventional method i.e. using memories for storing the permutation tables is silicon consuming. This work presents a 2-D transformation for WiMAX channel interleaver functions which reduces the overall hardware complexity to compute the interleaver addresses on the fly.  A fully re-configurable architecture for address generation in WiMAX channel interleaver is presented, which consume 1.1 k-gates in total. It can be configured for any block size and any modulation scheme in WiMAX. The presented architecture can run at a frequency of 200 MHz, thus fully supporting high bandwidth requirements for WiMAX.

  • 96.
    Ask, Per
    et al.
    Linköping University, Department of Biomedical Engineering, Physiological Measurements. Linköping University, The Institute of Technology.
    Öberg, Åke
    Linköping University, Department of Biomedical Engineering. Linköping University, The Institute of Technology.
    Pressure integrating transducer for oesophageal manometry.1979In: Medical and Biological Engineering and Computing, ISSN 0140-0118, E-ISSN 1741-0444, Vol. 17, no 3, p. 360-364Article in journal (Refereed)
    Abstract [en]

    A transducer has been designed that gives an integrated measure of the radial pressure profile at a specific level in the oesophagus. The oesophageal pressure is picked up by a semicylinder elastically connected to a transducer housing by means of a slotted semicylinder. The displacement of the semicylinder is sensed by a semiconductor transducer element. The transducer has a linear relation between static pressure and output voltage, flat frequency characteristic and low temperature drift.

  • 97.
    Ask, Per
    et al.
    Linköping University, Department of Biomedical Engineering, Physiological Measurements. Linköping University, The Institute of Technology.
    Öberg, Åke
    Linköping University, Department of Biomedical Engineering. Linköping University, The Institute of Technology.
    Tibbling, Lita
    Frequency content of esophageal peristaltic pressure.1979In: American Journal of Physiology, ISSN 0002-9513, E-ISSN 2163-5773, Vol. 236, no 3, p. E296-300Article in journal (Refereed)
    Abstract [en]

    Fourier analysis of esophageal peristaltic pressure waves was performed by computer fast Fourier transform. The highest power spectral density was obtained in the frequency range below 1 Hz. The Fourier analysis showed spectral components up to about 12 Hz in the upper esophageal sphincter (UES). The significance of different frequency components was investigated by low-pass filtering at different cut-off frequencies. A reduction in the amplitude of UES contractions was obtained at a cut-off frequency of 4 Hz, whereas the cut-off frequency of 8 Hz did not show any distortion. For perfused manometry systems, only a low-compliance perfusion pump will have sufficient bandwidth for accurate recording of esophageal peristaltic pressures.

  • 98.
    Aslam, Junaid
    Linköping University, Department of Electrical Engineering.
    Study and Comparison of On-Chip LC Oscillators for Energy Recovery Clocking2005Independent thesis Basic level (professional degree)Student thesis
    Abstract [en]

    This thesis deals with the study and comparison of on-chip LC Oscillators, used in energy recovery clocking, in terms of Power, Area of Inductor and change in load capacitance. Simulations show how the frequency of the two oscillators varies when the load capacitance is changed from 5pF to 105pF for a given network resistance. A conventional driver is used as a reference for comparisons of power consumptions of the two oscillators. It has been shown that the efficiency of the two oscillators can exceed that of a conventional driver provided the distribution network resistance is low and the on-chip inductor has a high enough Q value. Conclusions drawn from the simulations, using network resistances varying from 0Ω to 4Ω, show that the selection of the oscillator would depend on the network resistance and the amount of area available for the inductors.

    Download full text (pdf)
    FULLTEXT01
  • 99.
    ASLAM, UMAIR
    Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
    H.264 CODEC Blocks Implementation on FPGA2014Independent thesis Advanced level (degree of Master (Two Years)), 20 credits / 30 HE creditsStudent thesis
    Abstract [en]

    H.264/AVC (Advance Video Coding) standard developed by ITU-T Video Coding Experts Group(VCEG) and ISO/IEC JTC1 Moving Picture Experts Group (MPEG), is one of the most powerful andcommonly used format for video compression. It is mostly used in internet streaming sources i.e.from media servers to end users.

    This Master thesis aims at designing a CODEC targeting the Baseline profile on FPGA.Uncompressed raw data is fed into the encoder in units of macroblocks of 16×16 pixels. At thedecoder side the compressed bit stream is taken and the original frame is restored. Emphasis isput on the implementation of CODEC at RTL level and investigate the effect of certain parameterssuch as Quantisation Parameter (QP) on overall compression of the frame rather than investigatingmultiple solutions of a specified block of CODEC.

    Download full text (pdf)
    fulltext
  • 100.
    Athari, Emad
    et al.
    Linköping University, Department of Electrical Engineering.
    Lerenius, Petter
    Linköping University, Department of Electrical Engineering.
    Design and implementation of an SDR receiver for the VHF band2007Independent thesis Basic level (professional degree), 20 points / 30 hpStudent thesis
    Abstract [en]

    The purpose of this thesis work is to examine the possibility of building a software-defined radio (SDR) for the VHF-band. The goal is to accomplish this with as few components as possible, thus cutting down the size and the production cost.

    An SDR solution means that the sampling of the signal is done as close to the antenna as possible. The wide bandwidth needed in such a product is achieved by using SP Devices algorithm for time-interleaved ADCs. Two hardware prototypes and two versions of the software were designed and implemented using this technology.

    They were also analyzed within this thesis work. The results proved to be good, and the possibilities to produce a commercial software-defined radio receiver for the VHF-band are good.

    Download full text (pdf)
    FULLTEXT01
1234567 51 - 100 of 1212
CiteExportLink to result list
Permanent link
Cite
Citation style
  • apa
  • ieee
  • modern-language-association-8th-edition
  • vancouver
  • oxford
  • Other style
More styles
Language
  • de-DE
  • en-GB
  • en-US
  • fi-FI
  • nn-NO
  • nn-NB
  • sv-SE
  • Other locale
More languages
Output format
  • html
  • text
  • asciidoc
  • rtf